MASH ΣΔ modulators with a noise-shaped two-step ADC in the second stage

In this paper, a multi-stage noise-shaping (MASH) sigma-delta (ΣΔ) modulator is proposed to be used in low oversampling ratio (OSR) applications. It utilizes a noise-shaped two-step (NSTS) analog-to-digital converter (ADC) in the second stage and benefits its inter-stage gain to provide an extra attenuation of the quantization noise such that the same specifications of a traditional modulator are achieved but with a lower order of noise-shaping. Furthermore, large number of bits is resolved in the second stage while equal number of comparators is used. Compared to the single-loop NSTS ADC, in the proposed structure, the complexity problem of the feedback path and coefficient spreading are eliminated. As an example, a MASH 2-1 sigma-delta modulator has been designed and simulated in a 90 nm CMOS process using Spectre. The achieved resolution is 13.44 effective number of bits in 6.25 MHz signal bandwidth while consuming 19.6 mW power from a single 1 V supply. The sampling frequency is 100 MHz and the simulated figure of merit is 141 fJ/conv-step which shows the efficiency of the proposed modulator.     

一个用于GSM的80dB动态范围Σ-Δ调制器

设计了一个用于GSM系统的Sigma-Delta调制器. GSM系统要求信号带宽大于200kHz，动态范围大于80dB. 为了能取得较低的过采样率以降低功耗，采用了级联结构（MASH）来实现，与单环高阶结构相比，它具有稳定及易于实现的优点. 设计工作时钟为16MHz，过采样率为32，基带带宽为250kHz，电路仿真可以达到最高82dB的SNDR和87dB的动态范围. 芯片采用SMIC 0.18μm工艺进行流片，面积为1.2mm×1.8mm. 芯片测试效果最高SNDR＝74.4dB，动态范围超过80dB，测试结果与电路仿真结果相近，达到了预定的设计目标. 芯片工作在18V电源电压下，功耗为16.7mW.     

Architectures and design considerations for wireline ΣΔ modulators beyond ADSL

In this paper we discuss design considerations for sigma–delta modulators (ΣΔMs) aimed at high-linearity high-speed A/D conversion, as required in emerging wireline access applications. In order to achieve resolutions in the range of 12–15 bit with sufficiently low oversampling ratio, we analyze the performance of a family of high-order cascade architectures in a low-voltage deep-submicron scenario. We show that, after proper architecture selection, guided by a simple power estimation method, these ΣΔMs are good candidates to achieve ADSL performances in coming CMOS processes. Experimental results on a prototype for ADSL+ applications designed in 2.5-V 0.25-μm CMOS suggest the possibility of programming or reusing the design for other telecom applications, thanks to the easiness to expand or shrink this family of cascade ΣΔMs to other orders. Estimated performance of the adapted prototype for ISDN, SDSL, and VDSL applications provides promising results.     

基于matlab的一种高精度级联Sigma-Delta调制器的结构设计

过采样技术给在VLSI领域的高精度数模转化器的实现提供帮助.该文提供了一个在时间上连续的2-2-2级联Sigma-Delta调制器结构设计.该级联调制器由3级二阶振荡环路滤波器,1-bit量化器和反馈部分的数模转化器组成.在MATLAB环境下,通过大量仿真验证最后得出:在采样率为50 MHz、5V工作电压、过采样比为32的条件下,利用CMOS 0.18μm 工艺,该调制器其SQNR为87 dB.     

Sigma-Delta小数分频频率综合器系统建模和仿真

行为级仿真平台的建立,可以对小数频率综合器的设计提供快速全面的时域仿真.重点分析了2/3多模可编程分频器和MASH结构调制器电路,并给出了一种计算环路滤波器参数的新型工程方法.建立了的Simulink仿真模型,可用于检验电路结构的正确性.     

一种GSM手机发射机数字模块的设计

设计了一种GSM射频芯片的锁相环式直接调制发射机的数字模块,完成了对基带数据的差分编码,高斯滤波,对信道码的处理,多级噪声整形,给锁相环提供分频比,并实现了对发射和接收信道的选择。通过Matlab建模仿真,完成对各个模块的结构设计,通过RTL级代码设计和编写相应的testbench进行功能验证,在Modelsim下进行仿真,实现了预定要求。在实践当中,通过了TSMC0.18μm的CMOS工艺,实现了CHRF06/GSM/E-GSMDCS/PCS射频芯片的发射数字部分的功能。     

一个用于GSM的80dB动态范围∑-Δ调制器

设计了一个用于GSM系统的Sigma-Delta调制器．GSM系统要求信号带宽大于200kHz，动态范围大于80dB．为了能取得较低的过采样率以降低功耗，采用了级联结构（MASH）来实现，与单环高阶结构相比，它具有稳定及易于实现的优点．设计工作时钟为16MHz，过采样率为32，基带带宽为250kHz，电路仿真可以达到最高82dB的SNDR和87dB的动态范围．芯片采用SMIC0．18μm工艺进行流片，面积为1．2mm×1．8mm．芯片测试效果最高SNDR=74．4dB，动态范围超过80dB，测试结果与电路仿真结果相近，达到了预定的设计目标．芯片工作在1．8V电源电压下，功耗为16．7mW．     

∑-△调制器的六阶噪声整形算法

文章介绍了SDMADC的单一环路和MASH两种结构的优缺点.通过对过采样理论和噪声整形原理的分析,来满足设计的要求推导出六阶MASH算法.为了降低过采样率,同时提高调制器的动态范围和信噪比,可以采用增加积分器的个数,考虑合理的级数,采用三级MASH(2-2-2)结构,采用单比特量化,通过增加调制器的阶数,来满足设计的要求.采用MATLAB进行了仿真,提供一种Sigma-DeltaADC在算法设计中的解决方案.     

一种2-1-1型MASH ∑-△调制器的系统设计

∑-△调制器的结构日趋复杂,用行为级模型进行仿真对提高设计效率来说是十分必要的。首先,文章讨论了开关电容∑-△调制器几种重要的非理想因素,例如时钟抖动、开关引起的非线性、开关热噪声、运放的非理想因素（等效输入噪声、有限直流增益、有限带宽、摆率和有限输出摆幅）,并且相应给出了在MATLAB／SIMULINK环境下创建的行为级模型。然后,文章基于上述模型给出了一个2-1-1MASH∑-△调制器行为级设计的例子。在给定过采样率为64的条件下,采样频率19．2MHz,调制器动态范围95dB,峰值信噪比94dB。     

Effective and equivalent doses for CT head examinations calculated using the voxelized phantoms MASH and FASH

The voxelized phantoms MASH and FASH have been used for calculating conversion coefficients (CCs) for a specific CT head examination performed in a specific Toshiba CT scanner. The X-ray spectrum was selected according to the concordance between the calculated C_100,c and measured C_100,c. For 120 kV, the X-raytbc code presented the smaller deviation, equal to −7.11%. Finally, effective doses calculated for the voxelized phantoms MASH and FASH were 6.1 and 4.5, respectively, smaller than the effective dose obtained though the European guidelines on quality criteria for computed tomography.