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Systematic designs to achieve normally-off operation and improved device performance for Al0.26Ga0.74N/AlN/GaN high electron mobility transistors (HEMTs) grown on a Si substrate are investigated in this work. The step-by-step approach includes: (1) devising a thin AlGaN/AlN composite barrier, (2) introducing fluoride ions within the active region by using CF4 plasma treatment, (3) growing the Al2O3 oxide passivation layers within gate-drain/source regions by using a cost-effective ozone water oxidization technique, and (4) integrating a metal-oxide-semiconductor gate (MOS-gate) design with high-k Al2O3 gate dielectric. Devices with four different evolutionary gate structures have been compared and studied. Variations of threshold voltage (Vth), Hooge coefficients (αH), maximum drain-source current density (IDS, max), maximum extrinsic transconductance (gm, max), gate-voltage swing (GVS) linearity, two-terminal gate-drain breakdown/turn-on voltages (BVGD/Von), on/off current ratio (Ion/Ioff), and high-temperature characteristics up to 450 K are also investigated. 相似文献
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Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET 总被引:1,自引:0,他引:1
Hemant Pardeshi Sudhansu Kumar Pati Godwin Raj N Mohankumar Chandan Kumar Sarkar 《半导体学报》2012,33(12):124001-7
We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (Vt), Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the Ioff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications. 相似文献
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Since it is naturally normally-off, the hybrid AlGaN/GaN MOS-HEMT has a tremendous potential for an advanced GaN-based power switch. An analytical model for the hybrid AlGaN/GaN HEMT on-resistance is presented in this paper. The methodology presented here can aid the designers to understand the physics and to electrically characterize the new generation of GaN based devices. The models proposed here can also easily be implemented in TCAD simulation packages where models for GaN devices are not mature. 相似文献
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The letter reports normally-off device characteristics of Al0.26Ga0.74N/AlN/GaN oxide-passivated high electron mobility transistors (HEMTs) and metal-oxide-semiconductor HEMTs (MOS-HEMTs) grown on a Si substrate. Al2O3 was formed as the surface passivation oxide or gate dielectric on a thin AlGaN barrier layer by using a cost-effective ozone water oxidization technique. CF4 plasma was used to enable normally-off operation. For the gate dimensions of 1×100 µm2, the present oxide-passivated HEMT and MOS-HEMT (a control Schottky-gate HEMT) have demonstrated superior on/off-current ratio (Ion/Ioff) of 2.5×106 and 1×107 (3.9×103), maximum extrinsic transconductance (gm, max) of 154 and 175 (120) mS/mm, maximum drain-source current density (IDS, max) of 312 and 349 (300) mA/mm, two-terminal gate-drain breakdown voltage (BVGD) of −80 and −140 (−36) V, turn-on voltage (Von) of 1.2 and 1.3 (1) V, and three-terminal on-state breakdown voltage (BVDS) of 93 and 109 (48) V. Excellent BVGD and BVDS enhancements of 122% (288%) and 94% (127%) are achieved in the present oxide-passivated HEMT (MOS-HEMT) design. 相似文献
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G. Toulon I. Corts F. Morancho E. Hugonnard-Bruyre B. Villard W.J. Toren 《Solid-state electronics》2011,61(1):111-115
In this paper, we have studied the effect of systematic downscaling of MOS channel length of the performance of the hybrid GaN MOS-HEMT with numerical simulations. The improvement in on-state conduction, together with concomitant short channel effects, including drain induced barrier lowering (DIBL) is quantitatively evaluated. A specific on-resistance of 2.1 mΩ cm2 has been projected for a MOS channel length of 0.38 μm. We also have assessed the impact of high-k gate dielectrics, such as Al2O3. In addition, we have found that adding a thin GaN cap layer on top of AlGaN barrier can help reducing short channel effects. 相似文献
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In this paper, a compact channel noise model for gate recessed enhancement mode GaN based MOS-HEMT which is valid for all regions of operation is proposed. The compact noise model consists of high frequency thermal noise and low frequency flicker noise. The drain current, which is one of the most important parameters for compact noise model is developed by incorporating interface and oxide traps, mobility degradation due to vertical electric field, velocity saturation effect and self-heating effect. The flicker noise model is derived by considering mobility and carrier fluctuation due to traps present in both oxide and interface layer. The thermal noise and flicker noise models are validated by comparing the results with TCAD simulation and experimental results from literature respectively. Effect of thermal and flicker noise power spectral density (PSD) variation with different oxide thickness has also been analyzed. 相似文献
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YuanZheng Yue Yue Hao Qian Feng JinCheng Zhang XiaoHua Ma JinYu Ni 《中国科学E辑(英文版)》2009,52(9):2762-2766
We report on a GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) using atomic-layer deposited (ALD)
Al2O3 as the gate dielectric. Through further decreasing the thickness of the gate oxide to 3.5 nm and optimizing the device fabrication
process, a device with maximum transconductance of 150 mS/mm was produced. The drain current of this 0.8 μm gate-length MOS-HEMT
could reach 800 mA/mm at +3.0 V gate bias. Compared to a conventional AlGaN/GaN HEMT of similar design, better interface property,
lower leakage current, and smaller capacitance-voltage (C-V) hysteresis were obtained, and the superiority of this MOS-HEMT
device structure with ALD Al2O3 gate dielectric was exhibited.
Supported by the National Natural Science Foundation of China (Grant No. 60736033) and the National Basic Research Program
of China (“973“) (Grant No. 51327020301) 相似文献
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