Effect of epitaxial realignment on the leakage behavior of arsenic-implanted,as-deposited polycrystalline Si-on-single crystal Si diodes

When dopants are indiffused from a heavily implanted polycrystalline silicon film deposited on a silicon substrate, high thermal budget annealing can cause the interfacial “native” oxide at the polycrystalline silicon-single crystal silicon interface to break up into oxide clusters, causing epitaxial realignment of the polycrystalline silicon layer with respect to the silicon substrate. Anomalous transient enhanced diffusion occurs during epitaxial realignment and this has adverse effects on the leakage characteristics of the shallow junctions formed in the silicon substrate using this technique. The degradation in the leakage current is mainly due to increased generation-recombination in the depletion region because of defect injection from the interface.     

Formation of low-resistivity poly-Si and SiNx films by Cat-CVD for ULSI application

In this paper, bulk-Si metal–oxide–semiconductor field effect transistors (MOSFETs) are fabricated using the catalytic chemical vapor deposition (Cat-CVD) method as an alternative technology to the conventional high-temperature thermal chemical vapor deposition. Particularly, formation of low-resistivity phosphorus (P)-doped poly-Si films is attempted by using Cat-CVD-deposited amorphous silicon (a-Si) films and successive rapid thermal annealing (RTA) of them. Even after RTA processes, neither peeling nor bubbling are observed, since hydrogen contents in Cat-CVD a-Si films can be as low as 1.1%. Both the crystallization and low resistivity of 0.004 Ω·cm are realized by RTA at 1000 °C for only 5 s. It is also revealed that Cat-CVD SiN_x films prepared at 250 °C show excellent oxidation resistance, when the thickness of films is larger than approximately 10 nm for wet O₂ oxidation at 1100 °C. It is found that the thickness required to stop oxygen penetration is equivalent to that for thermal CVD SiN_x prepared at 750 °C. Finally, complementary MOSFETs (CMOSs) of single-crystalline Si were fabricated by using Cat-CVD poly-Si for gate electrodes and SiN_x films for masks of local oxidation of silicon (LOCOS). At 3.3 V operation, less than 1.0 pA μm⁻¹ of OFF leakage current and ON/OFF ratio of 10⁷–10⁸ are realized, i.e. the devices can operate similarly to conventional thermal CVD process.     

Treatment of Point Defects in Nanowire MOSFETs Using the Nonequilibrium Green’s Function Formalism

A program to numerically simulate point defects in nanowire metal-oxide-semiconductor field-effect transistors is described. The simulation scheme is based on the non-equilibrium Green’s function method self-consistently being obtained via the resolution of 3D Poisson’s equation. A tight-binding hamiltonian is used and the point defect is characterized by a macroscopic coulombic tail treated in the mode-space approach, plus a short range on-site perturbation potential energy, treated exactly. The effect on internal quantities and on the transistor characteristics is studied as a function of the strength and the location of the defect potential. Subthreshold current is found to vary in a factor 10 according to the position of the impurity.Also With Institut Universitaire De France (IUF).     

Thirty Years of Monte Carlo Simulations of Electronic Transport in Semiconductors: Their Relevance to Science and Mainstream VLSI Technology

We review briefly some aspects of the history of Monte Carlo simulations of electronic transport in semiconductors. In the early days their heavy computational cost rendered them suitable only to study problems of pure physics, as simpler models provided the answers necessary to design ‘electrostatically good’ devices. Now that scaling has taken another meaning (i.e., looking for alternative materials, crystal orientations, device geometries, etc.), Monte Carlo simulations may gain popularity once more, since they allow an efficient and reliable evaluation of speculative ideas. We show examples of both aspects of the results of Monte Carlo work.     

A 2D Transconductance and Sub-threshold behavior model for triple material surrounding gate (TMSG) MOSFETs

A 2D analytical model for transconductance, Sub-threshold current and Sub-threshold swing for Triple Material Surrounding Gate MOSFET (TMSG) is presented in this paper. Based on the solution of two dimensional Poisson equation, the physics based model of sub-threshold current of the device is derived. The model also includes the effect of gate oxide thickness and silicon thickness on the sub-threshold swing characteristics. Transconductance to drain current ratio of the triple material surrounding gate is calculated since it is a better criterion to access the performance of the device. The effectiveness of TMSG design was scrutinized by comparing with other triple material and dual material gate structures. Moreover the effect of technology parameter variations is also studied and proposed. This proposed model offers basic guidance for design of TMSG MOSFETs. The results of the analytical model are compared with the MEDICI simulation results thus providing validity of the proposed model.     

新型槽栅MOSFETs的特性

采用SIVALCO软件对槽栅与平面器件进行了仿真对比分析,结果表明槽栅器件能够有效地抑制短沟道及热载流子效应,而拐角效应是槽栅器件优于平面器件特性更加稳定的原因.对自对准工艺下成功投片所得沟道长度为140nm的槽栅器件进行测量,结果有力地证明了槽栅器件较平面器件的优越性.     

The Use of Quantum Potentials for Confinement and Tunnelling in Semiconductor Devices

As MOSFETs are scaled to sub 100 nm dimensions, quantum mechanical confinement in the direction normal to the silicon dioxide interface and tunnelling (through the gate oxide, band-to-band and from source-to-drain) start to strongly affect their characteristics. Recently it has been demonstrated that first order quantum corrections can be successfully introduced in self-consistent drift diffusion-type models using Quantum Potentials. In this paper we describe the introduction of such quantum corrections within a full 3D drift diffusion simulation framework. We compare the two most popular quantum potential techniques: density gradient and the effective potential approaches, in terms of their justification, accuracy and computational efficiency. The usefulness of their 3D implementation is demonstrated with examples of statistical simulations of intrinsic fluctuation effects in decanano MOSFETs introduced by discrete random dopants. We also discuss the capability of the density gradient formalism to handle direct source-to-drain tunnelling in sub 10 nm double-gate MOSFETS, illustrated in comparison with Non-Equilibrium Green's Functions simulations.     

二维量子力学效应对阈值电压的影响

在亚50nm的MOSFET中,沿沟道方向的量子力学效应严重影响了器件性能.基于WKB理论,考虑MOSFET中该效应对垂直沟道方向上能级的影响,引入了其时阈值电压的修正.继而对沟道方向的子带作了抛物线近似并进行了数值拟合,从而建立了一个考虑量子力学效应的全解析模型.由此模型可以得到二维量子力学修正和沟道长度以及其它器件参数的关系.与数值模拟结构比较可以得出如下结论:在亚50nm的MOSFET中,量子力学效应引入了阈值电压的修正是不可忽略的.且此全解析模型精度令人满意.     

采用绝缘型封装的沟道型功率MOSFET在低压车用驱动电路中的应用

本文介绍了功率半导体器件的一个新家族，即绝缘型封装的低压沟道型MOSFET：对MOSFET和封装技术做了一个简单介绍。由此可以衍生出几种器件和功率等级和特性。另外对这些新器件的典型运用作了一个介绍：如用在作为汽车辅助驱动电路的变换器中及用电池供电的运输工具中。     

Fabrication of Strained-Si/Strained-Ge Heterostructures on Insulator

Ultrathin strained-Si/strained-Ge heterostructures on insulator have been fabricated using a bond and etch-back technique. The substrate consists of a trilayer of 9 nm strained-Si/4 nm strained-Ge/3 nm strained-Si on a 400-nm-thick buried oxide. The epitaxial trilayer structure was originally grown pseudomorphic to a relaxed Si_0.5Ge_0.5 layer on a donor substrate. Raman analysis of the as-grown and final transferred layer structures indicates that there is little change in the strain in the Si and Ge layers after layer transfer. These ultrathin Si and Ge films have very high levels of strain (∼1.8% biaxial tension and 1.4% compression, respectively), and are suitable for enhanced-mobility field-effect transistor applications.