Numerical simulations of specimen size and mismatch effects in ductile crack growth - Part II: Near-tip stress fields

The effect of ductile crack growth on the near tip stress field in two different specimen geometries has been investigated. For homogeneous specimens it is observed that the peak stress level increases with ductile crack growth. The effect is most pronounced up to about 1 mm of crack growth. For low and intermediate hardening there is a significant effect of specimen size on the stress level. In case of mismatch in yield stress, the simulations show that the increase in stress level in the material with the lower yield stress is of a similar magnitude as is the case for stationary cracks. In case of ductile crack growth deviation from the original crack plane occurs, the highest stresses are still found close to the interface, and not in front of the current crack tip.     

Development of a gap searching program for automotive body assemblies based on a decomposition model representation

Automobiles, aircraft, and ships require tremendously many parts to be assembled. For developing such large assemblies, most companies accelerate the design process by having many design engineers in different functional or sectional design groups working concurrently. However, interferences and gaps can be found when the parts and sub-assemblies of different design groups are to be assembled. These error cause design changes and additional repair processes, resulting in an unexpected increase in costs and time delays. While the interference problem has been resolved by digital mockup and concurrent engineering methodology, many cases of the gap problem in the automotive industry have been covered by temporary treatments when the gaps are small enough to be filled with sealants. This kind of fast fix can cause leakage into the engine chamber and passenger cabin when the gap size is too big for filling or when the sealant gets old, which can turn fatal. With this research, we have developed a program to automatically find gaps between the parts of an assembly so that design engineers can correct their designs before the manufacturing stage begins. By using the method of decomposition model representation, the program can visualize gaps between complex car body parts as well as estimate their volumetric information. It can also automatically define the boundary between a gap and the exterior space. Although we have reviewed the benefits of the program by applying it to car development, it can also be applied to aircraft and ship designs comprising several parts.     

Peer-exchange schemes to handle mismatch in peer-to-peer systems

A self-organizing peer-to-peer system is built upon an application level overlay, whose topology is independent of an underlying physical network. A well-routed message path in such systems may result in a long delay and excessive traffic due to the mismatch between logical and physical networks. In order to solve this problem, we present a family of Peer-exchange Routing Optimization Protocols (PROP) to reconstruct the overlay. It includes two policies: PROP-G for generic condition and PROP-O for optimized one. Both theoretical analysis and simulation experiments show that these two protocols greatly reduce the average latency of the overlay and achieve a better logical topology with low overhead. Their overall performance can be further improved if combined with other recent approaches. Specifically, PROP-G can be easily applied to both structured and unstructured systems without the loss of their primary characteristics, such as efficient routing and anonymity. PROP-O, on the other hand, is more efficient, especially in a heterogenous environment where nodes have different processing capabilities.

Study on residual stress in viscoelastic thin film using curvature measurement method

Using LSM (laser scanning method), the radius of curvature due to thermal deformation in polyimide film coated on Si substrate is measured. Since the polyimide film shows viscoelastic behavior, i.e., the modulus and deformation of the film vary with time and temperature, we estimate the relaxation modulus and the residual stresses of the polyimide film by measuring the radius of curvature and subsequently by performing viscoelastic analysis. The residual stresses relax by an amount of 10% at 100°C and 20% at 150°C for two hours.     

Accounting for variability in the design of circuits with organic thin-film transistors

We experimentally verify that the methodology to account for local parameter variations and transistor mismatch known in Si CMOS technologies can be transposed to organic thin-film transistor technologies, and we present a design case that makes use of design for variability. Transistor parameter variation decreases with the square root of the transistor footprint. As a consequence, Monte Carlo simulations which take this effect into account can be executed to better predict the final circuit yield. The design case in this work is an 8-bit, organic RFID transponder chip. The yield prediction by simulations corresponds to the finally observed circuit yield.     

Scaling of analog LDPC decoders in sub-100 nm CMOS processes

Analog implementations of digital error control decoders, generally referred to as analog decoding, have recently been proposed as an energy and area competitive methodology. Despite several successful implementations of small analog error control decoders, little is currently known about how this methodology scales to smaller process technologies and copes with the non-idealities of nano-scale transistor sizing. A comprehensive analysis of the potential of sub-threshold analog decoding is examined in this paper. It is shown that mismatch effects dominated by threshold mismatch impose firm lower limits on the sizes of transistors. The effect of various forms of leakage currents is also investigated and minimal leakage current to normalizing currents are found using density evolution and control simulations. Finally, the convergence speed of analog decoders is examined via a density evolution approach. The results are compiled and predictions are given which show that process scaling below 90 nm processes brings no advantages, and, in some cases, may even degrade performance or increase required resources.     

A low-complexity low-spurs digital architecture for wideband PLL applications

This paper presents a non-ideality analysis of the wideband frequency synthesizer, and proposes a new digital architecture for signal modulation and quantization. Using error masking strategy, this method can offer smaller routing area and less power consumption without sacrificing any system performance. Simulation results confirm the theoretical predictions. Finally, the design guidelines are derived to fulfill the customized synthesizer specifications.     

SAR A/D转换器中电容失配问题的分析

在逐次逼近型(SAR)A/D转换器的设计过程中,电容网络的匹配精度对A/D转换器系统精度有着至关重要的影响。详细推导了电容失配误差与A/D转换器精度的关系表达式,给出了严密的理论证明,为电路设计人员选择工艺、版图方式、电路结构和电容大小提供了有力的理论基础。此论证方式也适用于电阻网络等其他二进制加权网络的精度计算。     

Numerical simulations of specimen size and mismatch effects in ductile crack growth - Part I: Tearing resistance and crack growth paths

The Gurson-Tvergaard-Needleman (GTN) model has been used for detailed numerical simulations of the effects of specimen size and yield stress mismatch on ductile crack growth behaviour in two different finite specimen geometries. For deep cracked bending specimens the crack growth resistance, expressed through the far-field J, increases as the specimen size is reduced, most strongly seen in case of low hardening. An opposite effect can be seen to some extent for shallow cracked specimens loaded in tension for low and intermediate hardening. For the yield stress mismatch cases low hardening and bend loading are found to promote crack growth deviation away from the initial crack plane.     

Positioning of PV panels for reduction in line losses and mismatch losses in PV array

Partial shading decreases the power output of PV arrays due to mismatch losses. These losses are dependent on the shading pattern and the relative positions of shaded modules in the array. Various static and dynamic reconfiguration techniques have earlier been proposed to mitigate these losses. In an earlier proposed static reconfiguration technique, the power generation is enhanced by altering the physical location of the PV panels using a random Sudoku configuration without modifying the TCT (Total-Cross-Tied) based electrical connections. However, this arrangement faces drawbacks due to ineffective dispersion of shade and significant increase in wiring required. In this work, an optimal Sudoku arrangement to overcome these drawbacks is formulated. Further analysis indicate that the global peak of the optimal Sudoku based PV array occurs as the right most peak in the curve for most shading conditions, thus evidently obviating the need for complex MPPT (Maximum-Power-Point-Tracking) algorithms. The proposed configuration is compared with various other existing reconfiguration schemes in terms of power output and the comparison is presented. In addition, a general formulation is proposed to expand this pattern to any generic array. A strategy is also proposed to make such an interconnection practicable for very large size PV arrays.