嵌人式与独立存储器设计上的差异分析和研究

进入21世纪,随着集成电路的发展,SoC(System on Chip)片上系统应运而生。而作为SoC重要组成部分的嵌入式存储器,在SoC中所占的比重正逐步增加,并起着越来越重要的作用,那么嵌入式存储器与独立的存储器芯片在设计上存在着哪些差异?对此本文将以NOR型闪存为例在制造工艺的选取、衍生产品的设计、功耗与噪声、后端功能仿真、测试与修复等方面进行分析和研究。     

采用或非门设计最简逻辑电路的方法

给出了采用或非门、利用卡诺图设计最简逻辑电路的方法，并用实例论证这个方法是最简捷的方法，同时也具有一般性。在以CMOS为开关器件的数字集成电路芯片的设计中，由于或非门优于与非门，故应该使用所介绍的方法，直接采用或非门设计组合逻辑电路芯片。     

基于不同类型Flash-ROM的Bootloader设计

嵌入式微处理器片内资源越来越复杂以至于离开操作系统管理的嵌入式系统将无法有效运行。如何根据开发板硬件资源来设计嵌入式操作系统的引导程序（Bootloader）,无疑是一个重点和难点。介绍了具有不同固态存储类设备的嵌入式开发平台上的Bootloader的概念、主要任务和实现分析等。对比了NAND Flash和NOR Flash的主要异同。以加载ARM-Linux操作系统内核为例,阐述了基于TI TMS320DM6446嵌入式系统开发平台上利用NAND及NOR Flash两类Flash-ROM（闪存）引导加载操作系统的软件设计方法。     

栅侧壁隔离层对45nm NOR闪存栅极干扰的影响

为了研究侧壁隔离层对闪存器件可靠性的影响,分别制备了Si3N4和SiO2-Si3N4-SiO2-Si3N4 (ONON)复合层作为栅侧壁隔离层的45 nm或非闪存(NOR flash)器件,对编程后、循环擦写后的闪存器进行栅极干扰的测试,讨论了不同栅侧壁隔离层对栅极干扰的影响.结果表明,虽然纯氧化硅隔离层可减少NOR自对准接触孔(SAC)刻蚀时对侧壁隔离层的损伤,但其在栅极干扰时在氧化物-氮化物-氧化物(ONO)处有更高的电场,从而在栅干扰后阈值电压变化较大,且由于在擦写操作过程中会陷入电荷,这些电荷在大的栅极电压和长时间的栅干扰作用下均会对闪存器的可靠性产生负面的影响.ONON隔离层的闪存器无可靠性失效.因此以ONON作为侧壁隔离层比以纯氮化硅作为侧壁隔离层的闪存器件具有更好的栅干扰性能.     

基于NOR闪存设备的MTD驱动程序

uClinux系统下的闪存设备驱动程序开发,采用S3C44B0X处理器.使用Flash存储器接口电路、JFFS2文件系统,操作MTD芯片和硬件设备驱动的相关信息.并通过调用相关函数向系统加入和删除MTD原始设备、注册和注销原始设备的使用者.MTD在系统启动后自动识别支持CFI或JEDEC接口的FLASH芯片,之后通过查询命令读取CFI查询结构.     

Wavelet domain analysis for identification of vehicle axles from bridge measurements

Bridge weigh-in-motion (B-WIM) is a process by which the axle and gross vehicle weights of vehicles travelling at highway speeds can be determined from instrumented bridges. The traditional method of attaching strain transducers to the soffit of the bridge and placing axle detectors on the road surface has been replaced here by using additional transducers underneath the bridge for axle detection and nothing-on-the-road (NOR). This paper presents a wavelet based analysis of strain signals and shows the efficacy of using wavelets in pattern recognition of these signals. The transformed signals are used to identify axle passage and hence the vehicle velocity and the axle spacing. In addition to numerically generated strains, signals acquired from such a NOR instrumentation of a bridge in Slovenia have been analysed by the method of wavelet transformation to extract axle position information that was not readily detectable using existing methods.     

Parallel multipliers with NOR gates based on G-minimum adders

Based on the adders with a minimum number of NOR gates discussed in Ref. 1, parallel multiplers are designed in Ref. 2, using fewer gates, fewer connections, and faster operation than conventional multipliers based on carry-save adders. In this paper, parallel multipliers of NOR gates are designed, by expressing two numbers to be multiplied in the sign and magnitude representation unlike those in Ref. 2. The multipliers in this paper are advantageous over the carry-save adder-type multipliers known to date, in terms of the number of gates and connections.This work is supported in part by the National Science Foundation under Grant No. MCS77-09744 and MCS81-08505.     

嵌入式处理器AU1100的存储器接口设计

采用NOR Flash和NAND Flash设计嵌入式处理器AU1100的存储器接口.通过AU1100内嵌SDRAM总线控制器提供标准32位数据宽度总线接口,Flash直接挂接在静态总线上.软件设计中用于代码存储的NOR Flash作为NAND Flash的补充,YaFFS文件系统管理NAND Flash,并进行坏块屏蔽.用增强型ECC/EDC算法检验NAND Flash以减少NAND Flash的位反率,保证系统的安全性和可靠性.     

All-optical digital 4 × 2 encoder based on 2D photonic crystal ring resonators

The photonic crystals draw significant attention to build all-optical logic devices and are considered one of the solutions for the opto-electronic bottleneck via speed and size. The paper presents a novel optical 4 × 2 encoder based on 2D square lattice photonic crystals of silicon rods. The main realization of optical encoder is based on the photonic crystal ring resonator NOR gates. The proposed structure has four logic input ports, two output ports, and two bias input port. The photonic crystal structure has a square lattice of silicon rods with a refractive index of 3.39 in air. The structure has lattice constant ‘a’ equal to 630 nm and bandgap range from 0.32 to 044. The total size of the proposed 4 × 2 encoder is equal to 35 μm × 35 μm. The simulation results using the dimensional finite difference time domain and Plane Wave Expansion methods confirm the operation and the feasibility of the proposed optical encoder for ultrafast optical digital circuits.