Analysis of HBM ESD testers and specifications using a fourth-order lumped element model

This paper presents the general and analytical solution of a fourth-order lumped element model (LEM) to describe human body model (HBM) electrostatic discharge (ESD) testers including the main tester parasitic elements. The analytical fitting to the LEM of experimentally obtained HBM pulse data is a new scientifically justified tool to determine HBM tester parasitic elements. The impact of the test board capacitance on HBM testing is demonstrated and explained. Furthermore, the MIL 883C/3015.7¹ and EOS/ESD S5.1-1991² Standards on HBM testers are evaluated upon their selectivity to the test board capacitance. Finally, recommendations to improve HBM tester specifications regarding their selectivity to the parasitic test board capacitance are formulated     

A low power low area capacitor array based Digital to Analog Converter architecture

This paper presents a capacitor based Digital to Analog Converter architecture, which gives comparable performance with the conventional architecture with approximately half the total capacitance. The proposed architecture reduces the area and power dissipation in comparison with the conventional scheme. Further to these advantages, the proposed DAC architecture does not demand an additional reference voltage or an additional switching circuit. Closed form formulas to estimate the standard deviation of INL, DNL and the power consumption are derived. A comparison is also made between the standard architectures and the proposed architecture for the same unit capacitor, in addition to analyzing the capacitor parasitics and mismatches. These analytical comparisons are validated by simulating the proposed architecture and all the other conventional architectures for 10 bits with UMC 180 nm CMOS technology.     

A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization

CMOS differential cross-coupled LC oscillators are widely used due to their superior phase noise performance. Even though the number of circuit elements is small, the design process is not trivial due to the complicated trade-off between the phase noise and power consumption. Conventionally, cross-coupled oscillators can be constructed by using only PMOS or only NMOS devices or using both (CMOS). The topology selection is mostly based on either theoretical calculations or experimental (measurement/simulation) results on specific solution points reported in the literature; however, there is no comprehensive analysis on comparison of these topologies in the literature. Also, there are several efforts on improving the phase noise response such as conventional tail noise filtering (using a tail capacitor or LC filter) and sinusoidal tail shaping. Yet, the cost-performance effectiveness of such techniques has not been well-discussed in the literature. In this study, performances of different differential cross-coupled LC oscillators are examined using a parasitic-aware multi-objective RF circuit synthesis tool. PMOS, NMOS, and CMOS types of oscillators were synthesized and performances of those circuits were thoroughly demonstrated. The synthesis results were validated by performing post-layout simulations for different solutions located on the Pareto optimal front (POF). To observe the effect of the other layout parasitics, the CMOS oscillator was also optimized including a parasitic netlist of a drawn layout. The effect of using LC tank with centre-tapped inductor on oscillator performance was also investigated. Furthermore, effectiveness of several phase noise reduction techniques; tail capacitor filtering, tail LC filtering, and sinusoidal noise shaping were demonstrated and discussed in detail.