Monte-Carlo Simulation of Clocked and Non-Clocked QCA Architectures

We present a Monte Carlo simulation of two implementations of Quantum Cellular Automaton (QCA) circuits: one based on simple ground state relaxation and the other on the clocked cell scheme that has recently been proposed by Tóth and Lent. We focus on the time-dependent behavior of two basic circuits, a binary wire and a majority voting gate, and assess their maximum operating speed and temperature requirements for different sets of fabrication parameters.     

A novel design of 8-bit adder/subtractor by quantum-dot cellular automata

Application of quantum-dot is a promising technology for implementing digital systems at nano-scale. QCA supports the new devices with nanotechnology architecture. This technique works based on electron interactions inside quantum-dots leading to emergence of quantum features and decreasing the problem of future integrated circuits in terms of size. In this paper, we will successfully design, implement and simulate a new full adder based on QCA with the minimum delay, area and complexities. Also, new XOR gates will be presented which are used in 8-bit controllable inverter in QCA. Furthermore, a new 8-bit full adder is designed based on the majority gate in the QCA, with the minimum number of cells and area which combines both designs to implement an 8-bit adder/subtractor in the QCA. This 8-bit adder/subtractor circuit has the minimum delay and complexity. Being potentially pipeline, the QCA technology calculates the maximum operating speed.     

喹(噁)啉-2-羧酸标准物质的制备研究

建立了一种喹(噁)啉-2-羧酸(QCA)合成工艺路线,选择适当的方法对产品进行纯化,制备标准品候选物,并利用IR、UV、1 HNMR和MS技术对其进行定性鉴定.卡尔费休法和热重分析法分别用于水分和无机杂质的分析;建立优化了QCA主成分定值的高效液相色谱(HPLC)法,对含量进行测定;对喹(噁)啉-2-羧酸进行了均匀性、稳定性研究.结果表明,研制的喹(噁)啉-2-羧酸标准物质均匀性良好,稳定时间12个月,可以用于残留检测的定性和定量分析.     

量子元胞自动机器件和电路的研究进展

量子元胞自动机(QCA)是一种新颖的纳米技术,该技术不再通过电流或电压而是基于场相互作用进行信息的计算和传递。首先,综述了两种量子元胞自动机(EQCA和MQCA)器件的计算原理、基本逻辑门和时钟。指出了QCA元胞构成的不同线结构可在相同层交叉传递信号而不受影响。然后,进一步总结了制备QCA器件和功能阵列或电路的实验方法和材料,得出MQCA器件和分子EQCA器件的发展将使该器件逐步达到实际应用水平的结论。详细讨论了目前QCA器件和电路(尤其是存储单元结构)研究取得的重要进展以及面临的问题。提出了QCA器件未来理论和应用研究中的开放课题和方向。     

A new quantum-dot cellular automata full-adder

A novel expandable five-input majority gate for quantum-dot cellular automata and a new full-adder cell are presented. Quantum-dot cellular automata (QCA) is an emerging technology and a possible alternative for semiconductor transistor based technologies. A novel QCA majority-logic gate is proposed. This component is suitable for designing QCA circuits. The gate is simple in structure and powerful in terms of implementing digital functions. By applying these kinds of gates, the hardware requirement for a QCA design can be reduced and circuits can be simpler in level, gate counts and clock phases. In order to verify the functionality of the proposed device, some physical proofs are provided. The proper functionality of the FA is checked by means of computer simulations using QCADesigner tool. Both simulation results and physical relations confirm our claims and its usefulness in designing every digital circuit.     

Design metal-dot based QCA circuits using SPICE model

This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulating the basic logic gates such as inverter and majority voter. The proposed model makes it possible to design and simulate QCA combinational circuits and hybrid circuits of QCA and other NANO devices using SPICE. In the second half part of the paper, SET and QCA co-design methodology is proposed and SET is used as a readout interface of the QCA cell array. The SET and QCA hybrid circuit is a promising nano-scale solution.     

Analysis of missing and additional cell defects in sequential quantum-dot cellular automata

The defect characterization of sequential devices and circuits, implemented by molecular quantum-dot cellular automata (QCA), is analyzed in this paper. A RS-type flip–flop is first introduced; this flip–flop takes into account the timing issues associated with the adiabatic switching of this technology and its requirements. It is then shown that a D-type flip–flop can be constructed with an embedded QCA wire which extends over multiple clocking zones. The logic-level characterization of both flip–flop devices is provided. A single additional and missing cell defect model is assumed for molecular implementation. For sequential circuits, defect characterization is pursued. It is shown that defects affect the functionality of basic QCA devices, resulting mostly in unwanted inversion and majority voter acting as a wire at logic level. In this paper, it is shown that a device-level characterization of the defects and faults can be consistently extended to a circuit-level analysis.     

Design and Optimization of Full Comparator Based on Quantum‐Dot Cellular Automata

Quantum‐dot cellular automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power consumption in comparison with CMOS technology. This letter proposes an optimized full comparator for implementation in QCA. The proposed design is compared with previous works in terms of complexity, area, and delay. In comparison with the best previous full comparator, our design has 64% and 85% improvement in cell count and area, respectively. Also, it is implemented with only one clock cycle. The obtained results show that our full comparator is more efficient in terms of cell count, complexity, area, and delay compared to the previous designs. Therefore, this structure can be simply used in designing QCA‐based circuits.     

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.     

New modified-majority voter-based efficient QCA digital logic design

ABSTRACT

Quantum-dot cellular automata (QCA) is an emerging nanotechnology and a possible alternative solution to the limitation of complementary metal oxide semiconductor (CMOS) technology. One of the most attractive fields in QCA is the implementation of configurable digital systems. This article presents a novel multifunctional gate called the modified-majority voter (MMV). The proposed gate works on the explicit interaction of the cell characteristic property for the implementation of digital circuits. This prominent feature of the proposed gate reduces the maximum hardware cost and implements highly efficient QCA structures. To verify the functionality of the proposed gate, some physical proofs, truth table and computational simulation results are performed. These results assured the validity of the existence of the proposed gate. It also dissipates less energy which has been calculated under three separate tunnelling energy levels using the QCAPro tool. To prove the effectiveness of the proposed MMV gate, several optimal irreversible arithmetic circuits such as three-input XOR, half-adder and full-adder are proposed. The modular layouts are verified with the freely available QCADesigner tool version 2.0.3.