排序方式: 共有12条查询结果,搜索用时 15 毫秒
1.
针对3GPP LTE标准中的Turbo码,设计了一种基于最大后验概率算法的低功耗并行译码器.根据二次置换多项式交织器的整数数学特性,分解并行处理中每个译码器的交织地址为子码块地址和块内偏移地址,提出一种高效的递归计算子码块交织地址的算法,使得并行度可以为任意值,而不仅仅限于2的幂次;并依此设计了低复杂度的实时递归计算交织器的互连结构,以避免传统实现方法中对交织地址的存储,有效地简化了Turbo译码器本征信息处理的互连网络,减小了实现面积和功耗;最后从结构级进行优化设计,进一步减少面积和功耗.实验结果表明,在40nm的工艺下,约束工作电压为1.18V、时钟频率为282MHz,版图实现可以达到130Mb/s的吞吐量,且功耗仅为107mW,每次迭代能量效率为0.107nJ/bit. 相似文献
2.
本文提出一种可以用于lte小基站的turbo码解码器设计, 它支持LTE标准中的188种不同长度的TURBO码解码。设计采用了最多16路的并行解码,迭代次数可设定。解码器提采用了一种改进的软输入软输出设计。设计采用了轮流计算前向状态矩阵,和后项状态矩阵。这样可以缩短基二算法的关键路径,同时分支传输概率也可以直接用于计算不再需要保存。分组数据利用列地址映射,和行数据交换完成整个码的交织计算,利用相反的过程完成解交织计算。每个时钟都可以产生交织与解交织数据,用于解码和存储运算。 相似文献
3.
讨论有限域上置换多项式(PP)基本原理,将其中简单的二次置换多项式(QPP)应用在Turbo码的交织器中,给出满足置换条件且性能较优的交织器系数的搜索量度,同时给出相应二次逆置换多项式(QIPP)的计算方法。比较了QPP交织器与其他几种确定型交织器的性能。针对深空测控的实际要求,给出一种具体的Turbo码编译码方案。仿真结果表明:该方案能够达到设计要求,且易于工程实现。 相似文献
4.
流星余迹通信信道具有短时突发传输的特点,为了在有限的传输时间内尽可能多的传输有用信息,达到提高传输速率及改善系统可通量的目的,提出了一种适用于流余通信系统的网格编码调制(TCM)技术;将8PSK恒包络调制方式与TCM相结合以充分利用系统的发射功率;为了降低TCM算法的误码率,将传统TCM中的卷积编码替换为Turbo码,形成了TTCM-8PSK算法;通过选取性能优异的交织参数与码长进一步改善误码性能;在译码时对迭代的外部信息和分支转移概率进行加权处理,降低算法的复杂度;仿真结果表明:与常用的RS编码及BPSK/QPSK调制方式相比,TTCM-8PSK算法不仅使流余通信系统的可通量得到了提升,而且提高了传输可靠性,为下一代流余通信系统研制提供了理论基础。 相似文献
5.
提出了基于高次多项式无冲突交织器的Turbo码并行解码的优化实现方法,解码器采用MAX-Log-MAP算法,完成了从Matlab算法设计验证到RTL设计、FPGA验证,并在LTE无线通信链路中验证.设计的Turbo并行高速解码器半次迭代的效率为6.9 bit/cycle,在最高迭代为5.5次、时钟频率为309MHz下,达到207Mb/s的吞吐率,满足高速无线通信系统的要求,交织和解交织采用存储器映射方法.该设计节约了计算电路和存储量. 相似文献
6.
Shivani Verma 《International Journal of Electronics》2013,100(4):599-618
This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW – SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of ‘mod’ operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology. 相似文献
7.
In this paper, a high performance parallel turbo decoder is designed to support 188 block sizes in the 3rd generation partnership (3GPP) long term evolution (LTE) standard. A novel configurable quadratic permutation polynomial (QPP) multistage network and address generator are proposed to reduce the complexity of interleaving. This 2n-input network can be configured to support any 2i-input network. Furthermore, it can flexibly support arbitrary contention-free interleavers by cascading an additional specially designed network. In addition, an optimized decoding schedule scheme is presented to reduce the performance loss caused by high parallelism. Memory architecture and address mapping method are optimized to avoid memory access contention of small blocks. Moreover, a dual-mode add–compare–select (ACS) unit implementing both radix-2 and radix-4 recursion is proposed to support the block sizes that are not divided by 16. Implemented in 130 nm CMOS technology, the design achieves 384.3 Mbps peak throughput at clock rate of 290 MHz with 5.5 iterations. Consuming 4.02 mm2 core area and 716 mW power, the decoder has a 1.81 bits/cycle/iteration/mm2 architecture efficiency and a 0.34 nJ/bit/iteration energy efficiency, which is competitive with other recent works. 相似文献
8.
交织器的设计对提高Turbo码的性能有着重要的影响。首先研究了QPP交织器的设计原则,给出了具有良好S距离特性的QPP交织的设计方法。仿真结果表明:设计得到的QPP交织器的性能并不比通过随机搜索得到的一般S-随机交织器性能差。 相似文献
9.
Jae‐Hun Chung Heemin Park Chong S. Rim 《IEEJ Transactions on Electrical and Electronic Engineering》2015,10(1):70-74
Parallel processing and double‐flow methods, which are used to increase the speed of turbo‐code decoding, cause memory contentions. Although memory contentions due to parallel processing can be resolved by adopting the quadratic polynomial permutation (QPP) interleaver, the double‐flow method still causes memory contentions because of its read/write sequences from both ends of the input packets. Thus, we propose a modified architecture to resolve memory contentions for the double‐flow method to fit the QPP interleaver. In our experiment, the proposed method has a shorter decoding time and smaller hardware size compared the conventional method. A bit‐accurate simulation was performed, and hardware implementation with field‐programmable gate arrays (FPGAs) led to a high throughput of 80 Mbps. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. 相似文献
10.
研究了第三代合作伙伴计划长期演进技术(3GPP-LTE)中的二次置换多项式(QPP)交织器的硬件设计优化,提出了一种零延时、低复杂度的QPP交织器设计方案。该方案从算法层面出发简化了QPP交织器中定义的复杂运算。得益于算法优化的结果,优化后的QPP交织器能够以较低的代价映射到硬件电路上。结果表明:与一些传统方案相比,该方案设计的QPP交织器大大降低了硬件实现的复杂度,在SMIC 40nm工艺下,交织器的面积只有0.040mm~2。另外,所设计的QPP交织器具有零时延的特点,能够有效提高Turbo译码的译码效率。基于该交织器所设计的Turbo译码器能够稳定工作在400MHz下,译码速率达到572.85Mbps(10次半迭代),而译码器面积仅有0.82mm~2。 相似文献