Integrated Inductors Modeling for Library Development and Layout Generation

In this work we propose a modification to the conventional lumped equivalent circuit model for integrated inductors. Also the widely used parametric model is modified. The proposed models expand the frequency range where the integrated inductor behavior is accurately predicted. They are useful in developing automatic tools to assist the designers in selecting and automatically laying-out integrated inductors [1]. This work is based on measurements from integrated inductors fabricated in a standard silicon process.     

Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit

This paper presents a new low-cost RF BIST (Built-In Self-Test) scheme that is capable of measuring input impedance, gain, noise figure and input return loss for a low noise amplifier (LNA) in RF systems. The RF BIST technique requires an additional RF amplifier and two peak detectors, and its output is a DC voltage level. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the developed mathematical equations. Simulation results are presented for an LNA working at 5 GHz. Measurement data are compared with simulation results to validate the developed mathematical equations. The technique is simple and inexpensive. Jee-Youl Ryu received the BS and MS degrees in 1993 and 1997 from Pukyong National University in Electronic Engineering, Pusan, South Korea respectively. He also received the PhD degree in 2004 from Arizona State University in Electrical Engineering, Arizona, USA. He is currently with Samsung SDI Co., Ltd. His current research interests include RF IC design and testing, MMIC design and testing, analog IC design and testing, passives modeling, testing and analysis, and MEMS technology. Dr. Bruce Kim received the B.S.E.E. degree from the University of California, Irvine in 1981, the M.S. degree in electrical engineering from the University of Arizona in 1985, and the Ph.D. degree in electrical engineering from Georgia Institute of Technology in 1996. He was an Associate Professor at Arizona State University until 2005. Currently, he is an Associate Professor at The University of Alabama. His current research interests include RF IC testing, MEMS integration and VLSI circuits. He has been working on SiP testing technologies, package electrical modeling, and measurements of RF IC packages. Dr. Kim is a 1997 recipient of the National Science Foundation's CAREER Award and received the Meritorious Award from IEEE. He serves as the Chair of the IEEE CPMT Society TC-Electrical Test, associate editor of the IEEE Transactions on Advanced Packaging, associate editor of Design and Test of Computers, and program committee member of Electronic Components and Technology Conference. He is a senior member of IEEE.     

压控振荡器技术的回顾与展望

论述了压控振荡器技术发展的历程和趋势,介绍了SiGe压控振荡器技术.     

应用于无线传感器网络的低噪声放大器设计

给出一种基于SMIC0.13μm RFCMOS工艺、应用于无线传感器网络2.4GHz的低噪声放大器设计。设计目标为在2.43GHz的中心频率下带宽为120MHz,并且增益分为高20dB、中10dB及低0dB三档可调。电路采用功率和噪声优化技术,输入端采用片外电感匹配,输入输出都匹配到50Ω阻抗。在Cadence Spectre仿真环境下的后仿真结果表明:高增益时S21为21.2dB而噪声系数为0.5dB,S11为-29.8dB,S22为-20.7dB。电路在1.2V电源电压下的工作电流约为6mA。     

2-GHz CMOS射频低噪声放大器的设计与测试

本文采用CMOS工艺,针对无线通信系统前端(Front-end)的低噪声放大器进行了分析、设计、仿真和测试.测试结果表明,该放大器工作在2.04-GHz的中心频率上,3dB带宽约为110MHz,功率增益为22dB,NF小于3.3dB.测试结果与仿真结果能够很好地吻合.     

低压中和化CMOS差分低噪声放大器设计

以设计低电压LNA电路为目的,提出了一种采用关态MOSFET中和共源放大器输入级栅漏寄生电容Cgd的CMOS差分低噪声放大器结构.基于该技术,采用0.35μmCMOS工艺设计了一种工作在5.8GHz的低噪声放大器.结果表明,在考虑了各种寄生效应的情况下,该低噪声放大器可以在0.75V的电源电压下工作,其功耗仅为2.45mW.在5.8GHz工作频率下:该放大器的噪声系数为2.9dB,正向增益S21为5.8dB,反向隔离度S12为-30dB,S11为-13.5dB.     

领先的RFIC低成本测试方案

主流RFIC的高频率,高带宽,多射频端口的特点对现在的RFATE系统构成了不小的挑战,以模块化架构为基础的RFATE架构凭借丰富的射频端口资源、高效的并行测试构架、人性化的操作界面,以及先进的测试板为复杂RFIC提供了低成本测试解决方案。     

应用于无线传感器网络低噪声放大器的设计

本文给出一种应用于无线传感器网络射频前端低噪声放大器的设计,采用SMIC0．18μmCMOS工艺模型。在CadenceSpectre仿真环境下的仿真结果表明：该低噪声放大器满足射频前端的系统要求,在2．45GHz的中心频率下增益可调,高增益时,噪声系数为2．9dB,输入P1dB压缩点为-19．8dBm,增益为20．5dB;中增益时,噪声系数为3．6dB,输入P1dB压缩点为-15．8dBm,增益为12．5dB;低增益时,噪声系数为6．0dB,输入P1dB压缩点为-16．4dB,增益为2．2dB。电路的输入输出匹配良好,在电源电压1．8V条件下,工作电流约为6mA。     

具有高可调增益范围的CMOS宽带中频调制器

利用TSMC 0 .2 5 μmCMOS混合工艺 ,针对超外差结构的无线宽带收发器 ,实现了一个能够工作在 5 0～6 0 0MHz的中频调制器 ,并对该调制器进行了仿真和测试。由于该调制器在输出端采用了一个具有高可调增益范围而且鲁棒性能好的可变增益放大器 (VGA) ,从而使得该调制器具有超过 70dB的增益可调范围。测试结果表明 ,该调制器能够工作在 5 0～ 6 0 0MHz的频率上 ,输出功率为 - 81～ - 10dBm ,最小增益的输出噪声为 - 130dBm/ Hz,最大增益的输出P1dB点为 - 4 .3dBm ,在 3V的电源电压下 ,电流功耗为 32mA。     

智能门禁控制器的设计与实现

门禁控制器是门禁控制系统的核心,开发周期长,通用性差。在此利用现有读卡设备实现门禁控制器的设计,用户只需选用不同的读卡设备就可以实现不同卡的读取,对软件做适当修改,以满足不同门禁系统的需求,缩短了开发周期,提高了门禁控制器的通用性。在此还提供了多种开锁方式,方便用户的进出。在小区门禁系统中的应用证明,该门禁控制器运行稳定,可靠性高。