Surface mount digital package reliability

This paper compares the reliability of four surface mount package styles with the standard through-hole package. Three test boards were fabricated and subjected to environmental and electrical stresses. The relative package performances of SOICs, butt-soldered DIPs, surface mounted DIPS, and through-hole DIPs were found to be equal when subjected to stresses exceeding those expected in normal use. PLCC packages were found to be slightly less reliable in humidity environments than the other packages.     

Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes, e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.     

MEMS加速计的SOIC封装技术研究

文中通过研究MEMS（微机电系统）加速计在SOIC封装（小外形集成电路封装）下的特性,针对MEMS芯片断裂故障的原因分析了影响PPM（百万分比的缺陷率）性能的主要封装工艺步骤。其中感应单元固晶胶的硬度是引起芯片断裂的主要参数,通过反向工程确定了可以同时满足感应单元固有频率和封装可靠性要求的固晶材料。在试验中采用固晶胶E后,MEMS加速计的SOIC封装呈现出更加强韧的特性。此研究对于改善MEMS加速计的PPM性能有一定参考价值。