Reliability studies of MOCVD TiSiN and EnCoRe Ta(N)/Ta

Passivated single damascene copper SiO₂ damascene lines were evaluated in combination with TiSiN and Ta(N)/Ta diffusion barriers. Leakage current, breakdown and time-dependent dielectric breakdown properties were investigated on a wafer level basis for temperatures ranging between room temperature and 150 °C. It is found that the leakage performance of the wafers with a TiSiN barrier is better at room temperature, but at 150 °C the performance levels out with Ta(N)/Ta. Time-dependent dielectric breakdown measurements at 150 °C show that the lifetime of the interconnect is higher with the selected Ta(N)/Ta barrier than for TiSiN.     

HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

Introduction High- k gate dielectrics have been extensivelystudied as alternates to conventional gate oxide( Si O2 ) due to the aggressive downscaling of Si O2thickness in CMOS devices,and hence the exces-sive gate leakage.Hf O2 has emerged as one...     

One Method for Fast Gate Oxide TDDB Lifetime Prediction

提出了一种快速推算栅极氧化膜TDDB寿命的新方法.该方法可以用于对工艺的实时监控.通常情况下,为了得到栅极氧化膜在器件使用温度下的TDDB寿命,必须得到三个在一定温度下的不同电压下的TDDB寿命.然后使用一定模型(E模型或者1/E模型)和这个三个寿命推算出氧化膜在器件使用温度下的寿命.比较常用的是E模型.但是为了保证使用E模型推得的寿命的准确性,必须尽量使用较低电压下的寿命来推算想要的寿命.显然,为了获得低电压下的TDDB寿命,必须花费相当长的测试时间(甚至1个月).这对于工艺的实时监控来说,是不能接受的.文中提出一种新的推算栅氧化膜TDDB寿命的方法.运用该方法,可以快速、准确获得栅氧化膜的TDDB寿命,而花费的测试时间不到普通方法的1/1000000.在该方法中,巧妙地同时利用了1/E模型和E模型.     

衬底热空穴导致的薄栅介质经时击穿的物理模型研究1

该文定量研究了热电子和空穴注入对薄栅氧化层击穿的影响,讨论了不同应力条件下的阈值电压变化,首次提出了薄栅氧化层的经时击穿是由热电子和空穴共同作用的结果,并对上述实验现象进行了详细的理论分析,提出了薄栅氧化层经时击穿分两步。首先注入的热电子在薄栅氧化层中产生陷阱中心,然后空穴陷入陷阱导致薄栅氧击穿。     

薄栅氧化层斜坡电压TDDB寿命评价

随着超大规模集成电路的不断发展，薄栅氧化层的质量对器件和电路可靠性的作用越来越重要。经时绝缘击穿（TDDB）是评价薄栅氧化层质量的重要方法。文章着重于薄栅氧化层TD-DB可靠性评价的斜坡电压试验方法的研究，基于斜坡电压实验，提取模型参数，分别利用线性场模型和定量物理模型，外推出工作电压下栅氧化层的寿命。通过分析斜坡电压实验时氧化层的击穿过程，提出斜坡电压实验时利用统一模型外推栅氧化层的寿命比较合适。     

TEM样品制备辅助研究介质层可靠性失效机理

研究了TEM样品制备条件对Cu/低k制程ILD TDDB失效样品及含更低介电常数(k=2.7)介质层样品的TEM成像质量的影响,发现在一定的样品制备条件下低介电常数介质的疏松特性可在TEM成像时得到增强显示,进而揭示了某Cu/低k制程ILD TDDB可靠性失效样品的失效机理为芯片制造过程中介质层沉积温度异常导致其疏松特性增强,介电常数降低,从而导致其电绝缘性能下降而引起TDDB可靠性测试项目失效.     

微电子生产工艺可靠性评价与控制

简要介绍了可靠性评估(REM)测试结构设计,并介绍了REM试验中与时问有关的栅氧化层击穿(TDDB)、热载流子注入(HCI)效应和电迁移(EM)效应的评价试验方法及实例。REM技术与工艺过程控制(PCM)、统计工艺控制(SPC)技术结合起来就可以实现对工艺的可靠性评价与控制,某集成电路生产公司将它应用于金属化工艺中．确定了工艺输入变量与电迁移可靠性的相关性,优化了金属化工艺试验条件,提高了金属化系统的抗电迁移能力。     

Full-chip wire-oriented back-end-of-line TDDB hotspot detection and lifetime analysis

Time-dependent dielectric breakdown (TDDB) has become an important cause of failure for inter-metal dielectrics (IMD) in integrated circuits as feature sizes continue to shrink and novel materials are introduced. Although many studies have been conducted to understand the underlying physics of this issue, not enough work has been focused on evaluating TDDB lifetime of practical chip designs in the physical design stage. This paper proposes a full-chip TDDB failure analysis methodology to evaluate lifetime and identify TDDB hotspots in VLSI layouts, which are essentially interconnect wires that have high failure risk due to TDDB. The proposed method features three new techniques compared to existing methods. First, we have developed a partitioning-based scheme to deal with scaling of full-chip analysis by partitioning the full chip layout into small tiles. Second, for each tile, the new method calculates a newly-introduced TDDB failure metric called TDDB Damage for vulnerable wires. Such a wire-oriented TDDB analysis is the first of its kind and is very amenable for physical design as the wires can be easily adjusted or re-routed for TDDB-aware optimization. Third, the new method considers the impact of the non-uniform electric field calculated using the finite element method (FEM), which significantly improves the accuracy of TDDB risk evaluation. Experimental results show that the proposed new TDDB analysis method is more accurate than a recently proposed full-chip TDDB analysis method in which electrical field is treated as a constant value. Additionally, the proposed method can analyze a practical VLSI layout in a few hours.     

应用于EEPROM的超薄SiO2 TDDB特性的研究

阐述了应用于ＥＥＰＲＯＭ中的超薄隧道氧化层随时间的击穿特性,比较和分析了不同的可靠性测试方法,并对超薄氧化层生长工艺的优化进行了探讨。     

Electrical characteristics and TDDB breakdown mechanism of N2-RTA-treated Hf-based high-κ gate dielectrics

This study investigates the effects of rapid thermal annealing (RTA) in nitrogen ambient on HfO₂ and HfSiO_x gate dielectrics, including their electrical characteristics, film properties, TDDB reliability and breakdown mechanism. The optimal temperature for N₂ RTA treatment is also investigated. The positive oxide trap charges (oxygen vacancies) in HfO₂ and HfSiO_x dielectric films can be reduced by the thermal annealing, but as the annealing temperature increased, many positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy level will be formed in the grain boundaries, degrading the electrical characteristics, and changing the breakdown mechanism. We believe that variation in the number of positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy levels is the main cause of the CV shift and difference in the breakdown behaviors between HfO₂ and HfSiO_x dielectrics. With respect to CV characteristics and TDDB reliability, the optimal temperature for N₂ RTA treatment is in the range 500-600 °C and 800-900 °C, respectively.