Testability-analysis driven test-generation of analogue cores

A new definition of the testability transfer factor for circuit components that provides better sensitivity with respect to parametric deviations is presented. New equations for the testability measures in a mixed-signal core are given. Testability analysis is used for test-pattern generation and for consideration of inserting wrapper cells. The simulation results show the effectiveness of the approach.     

嵌入式计算机的BIT设计与实现

依据嵌入式计算机组成特点,在可测试性设计中采用层次式测试硬件结构,通过分布式测试控制管理,实现从器件级、模块级到子系统级、系统级的逐级测试.在BIT测试中,以CPU测试为例解析了测试用例数据、用例过程、执行控制和判决的组织与实现. .     

标准测试存取口与边界扫描结构在印制板级与系统级实现的探讨

本文探讨中国电子行业标准“标准可测性总线”第一部分“标准测试存取口与边界扫描结构”在印制板级与系统级的实现问题。阐述了不要针床夹具借助边界扫描测试印制板上器件间互连的方法,综述了美国相应标准ＩＥＥＥ Ｓｔｄ １１４９．１公布前后提出和试行在印制板级和实验级实现的若干方法和方案,包括采用符合与不符合该标准的两种器件的混合型板和系统。初步探讨了实践中国电子行业标准“标准测试存取口与边界扫描结构”和开发     

Testing digital safety system software with a testability measure based on a software fault tree

Using predeveloped software, a digital safety system is designed that meets the quality standards of a safety system. To demonstrate the quality, the design process and operating history of the product are reviewed along with configuration management practices. The application software of the safety system is developed in accordance with the planned life cycle. Testing, which is a major phase that takes a significant time in the overall life cycle, can be optimized if the testability of the software can be evaluated. The proposed testability measure of the software is based on the entropy of the importance of basic statements and the failure probability from a software fault tree. To calculate testability, a fault tree is used in the analysis of a source code. With a quantitative measure of testability, testing can be optimized. The proposed testability can also be used to demonstrate whether the test cases based on uniform partitions, such as branch coverage criteria, result in homogeneous partitions that is known to be more effective than random testing. In this paper, the testability measure is calculated for the modules of a nuclear power plant's safety software. The module testing with branch coverage criteria required fewer test cases if the module has higher testability. The result shows that the testability measure can be used to evaluate whether partitions have homogeneous characteristics.     

软件的可测试性设计

软件产品开发规模的扩大和数量的增长迫切需要找到一种方法来增加软件测试的有效性。可测试性设计可以增强软件的可测试性,降低测试的强度。该文讨论了软件可测试性的特征和影响软件测试的因素,以及改进软件可测试性设计的几种方法。建议在软件开发的整个周期中融入软件的可测试性的设计。     

软件内建自测试中模板内容的研究和实现

软件内建自测试是软件测试和可测性设计研究领域中的一个新概念,其思想来源于硬件内建自测试BIST(BuildinSelfTest)。软件内建自测试为程序员提供一套预先设计好的模板,由模板对所编写的程序植入测试信息,实现软件内建自测试以解决软件测试难的问题。模板是软件内建自测试系统的基石,其内容关系到整个系统的性能和效果。具体讨论了模板的实现,根据软件故障模型对代码进行改装,从而减少程序出错的概率,同时为软件内建自测试系统中测试用例的生成提供了更丰富的信息。     

计算机辅助测试性设计中的测试性改善最大化问题研究

基于边界扫描的计算机辅助电路板测试性设计中,面临着“设计复杂性一定时,如何权衡设计使得测试性改善最大”的问题。文章首先建立了该问题的数学描述,然后提出了求解问题的优化算法。仿真实验表明,该算法能够得到较优化的电路板测试性设计方案。     

一种有效的八位MCU桶形移位器 BIST 电路

针对8位微控制器（MCU）数据通道中桶形移位器的可测试性问题，提出了一种新颖的确定性内置自测试（BIST）电路设计方案，并对其进行了验证。该方案采用5个D触发器，在16个测试时钟周期内产生16个测试矢量，可完成对8位桶形移位器100％故障覆盖率测试。本论文的电路设计方案也可应用于一般2^N位（N≥4）桶形移位器的可测试设计。     

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.     

A BIST-DFT technique for DC test of analog modules

Among test techniques for analog circuits, DC test is one of the simplest method for BIST application since easy to integrate test pattern generator and response analyzer are conceivable. Precisely, this paper presents such an investigation for a CMOS operational amplifier that is latter extended to active analog filters. Since the computation of fault coverage is still a controversy question for analog cells, we develop first an evaluation technique for optimizing the tolerance band of the measurements to test. Then, using some DFT solutions we derive single DC pattern and discuss the minimal number of points to test for the detection of defects. A response analyzer is integrated with a Built-in Voltage Sensor (BIVS) and provides directly a logic pass/fail test result. Finally, the extra circuitry introduced by this BIST technique for analog modules does not exceed 5% of the total silicon area of the circuit under test and detects most of the faults.