Mixed Mode VLSI Implementation of a Neural Associative Memory

A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. To keep the memory density as high as possible two design strategies are considered. First, the number of transistors per storage element is kept to a minimum. In this paper a circuit technique that uses a single 6-transistor cell for weight storage and analog signal processing is proposed. Second, the device precision has been chosen to a moderate level to save area as much as possible. Since device mismatch limits the performance of analog circuits, the impact of device precision on the circuit performance is explicitly discussed. It is shown that the device precision limits the number of rows activated in parallel. Since the input vector as well as the output vector are considered to be sparsely coded it is concluded, that even for large matrices the proposed circuit technique is appropriate and ultra large scale integration with a large number of connection weights is feasible.     

降低超大规模集成电路用高纯水中总有机碳的能量传递光化学模型

本文提出用185nm紫外线降低高纯水中总有机碳(TOC)的能量传递光化学模型.计算了水的流量、TOC的浓度、照射腔的尺寸与所需紫外光能量的关系,从而解决了在工程设计中185nm紫外灯的选择和计算方法.根据理论计算出的结果和实验十分一致,证实了本模型的正确性.使高纯水中的TOC由4200μg/l 降至0.3μg/l,是目前国内外高纯水中TOC浓度的最好水平.     

从ULSI芯片的性能能量效率展望21世纪信息电子学的发展

现行的ULSI正在并将继续沿着Moore定律高速发展.在其前进道路上会遇到哪些物理障碍,要解决哪些技术课题?当CMOS技术达到或接近其发展极限后,后续的信息电子学(包括纳电子学、bio-inspired电子学和量子信息处理等)前景又将如何?本文基于UISI芯片的性能能量效率观点,对相关问题进行讨论.     

MOVPE生产用高纯水中硅的去除

本文介绍了硅对砷化镓材料生长及有机金属化合物气相淀积(MOVPE)工艺中的影响和电脱盐(EDI)技术以及用EDI降低高纯水中硅浓度的机理和方法,通过大量实验比较不同制水设备脱硅效果,得出用EDI技术严格控制pH(8~11)时脱硅效果最好,能使高纯水中Si的浓度＜0.5μg/L,满足了MO源生产及MOVPE工艺用水中Si浓度<3μg/L的需要.     

SiO2/Ta界面反应及其对铜扩散的影响

利用磁控溅射方法在表面有SiO2层的Si基片上溅射Ta/NiFe薄膜,采用X射线光电子能谱(XPS)研究了SiO2/Ta界面以及Ta5Si3标准样品,并进行计算机谱图拟合分析.实验结果表明在制备态下在SiO2/Ta界面处发生了热力学上有利的化学反应:37Ta+15SiO2=5Ta5Si3+6Ta2O5,界面处形成更稳定的化合物新相Ta5Si3、Ta2O5.在采用Ta作阻挡层的ULSI铜互连结构中这些反应产物可能有利于对Cu扩散的阻挡.     

Challenges in advanced semiconductor technology in the ulsl era for computer applications

This paper provides a review of the capabilities, future directions, and technology challenges for semiconductor chips and packages as they apply to high performance and supercomputer applications. Semiconductor chip technology has resulted in dramatic device density improvements over the last 20 years. Scaling theory predicts that continued improvements will be possible if the technological problems associated with patterning, doping, interconnection, density, yield, and cost can be solved. The issues associated with these challenges are discussed. Finally the packaging needs to support advanced chip technologies are reviewed.     

ULSI化学机械抛光的研究与展望

随着半导体行业的飞速发展，集成电路特征尺寸的微细化，半导体薄膜表面的高平坦化对器件高性能、低成本、高成品率有着重要的影响。作为唯一能实现全局平坦化方法的化学机械抛光(CMP)，近年来发展迅速，应用广泛。文章综述了化学机械抛光技术的发展现状：包括化学机械抛光设备、抛光液、抛光机理模型及应用研究进展；在此基础上，对CMP下一步发展的方向及其应用前景进行了展望。     

300mm硅片精密化学机械抛光机几何参数优化(英文)

对于评价用于极大规模集成电路(ULSI)生产的300 mm硅抛光片的表面质量,需要关注两个关键参数即:SFQR和GBIR。在中国电子科技集团第四十五研究所研发的中国第一台最终化学精密抛光机的验证过程中,我们发现为了提高硅片表面的几何参数,必须监控抛光前硅片的形貌,并根据不同的硅片表面形貌来改变抛光头的区域压力。通过深入分析抛光前硅片的表面形貌,我们发现当硅片形貌为凹陷形状时,抛光后的硅片表面将严重恶化。由此,根据每个硅片不同的形貌,我们用特殊设计的抛光头来调整背压的区域分布,然后再进行抛光。最终,经过抛光头区域压力调整后的硅片几何参数比调整前得到了大幅提升,并已经能够满足我们的产品指标并可以用于生产。     

Barrier layers for Cu ULSI metallization

Barrier layers are integral parts of many metal interconnect systems. In this paper we review the current status of barrier layers for copper metallization for ultra-large-scale-integration (ULSI) technology for integrated circuits (ICs) manufacturing. The role of barrier layers is reviewed and the criteria that determine the process window, i.e. the optimum barrier thickness and the deposition processes, for their manufacturing are discussed. Various deposition methods are presented: physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), electroless deposition (ELD), and atomic layer CVD (ALCVD) for barrier layers implementation. The barrier integration methods and the interaction between the barrier and the copper metallization are presented and discussed. Finally, the common inspection and metrology for barrier layer are critically reviewed.