基于开关电流技术的连续小波变换的实现方法

开关电流技术是一种新的模拟抽样数据处理技术。开关电流电路具有一般电路不具有的优点，与标准数字CMOS工艺兼容。连续小波变换是分析非平稳信号的有力工具，在信号处理上有广泛的应用。本文提出用开关电流技术实现连续小波变换的方法，并用Matlab仿真证明了其理论可行性。     

16信道0.35μmCMOS/VCSEL光发射模块

研究了垂直腔面发射激光器 (VCSEL)及其列阵器件的光谱特性、调制特性、高频特性及与微电子电路的兼容性 ,将 1× 16的VCSEL与CMOS专用集成电路进行多芯片组装 (MCM ) ,混合集成为 16信道VCSEL光发射功能模块 .测试过程中 ,功能模块的光电特性及其均匀性良好 ,测量的 - 3dB频带宽度大于 2GHz.     

Characterization and optimization of copper chemical mechanical planarization

The feature scale planarization of the copper chemical mechanical planarization (CMP) process has been characterized for two copper processes using Hitachi 430-TU/Hitachi T605 and Cabot 5001/Arch Cu10K consumables. The first process is an example of an abrasive-free polish with a high-selectivity barrier slurry, while the second is an example of a conventional abrasive slurry with a low-selectivity barrier slurry. Copper fill planarization has been characterized for structures with conformal deposition as well as with bumps resulting from bottom-up fill. Dishing and erosion were characterized for several structures after clearing. The abrasive-free polish resulted in low sensitivity to overpolish and low saturation levels for dishing and erosion. Consequently, this demonstrated superior performance when compared to the International Technology Roadmap for Semiconductors (ITRS) 2000 roadmap targets for planarization. While the conventional slurry could achieve the 0.13-μm technology node requirements, the abrasive-free polish met the planarization requirements beyond the 0.10-μm technology node.     

光互连技术的研究现状及发展

本文首先总结了光学互连的主要实现途径，然后评述了光互连的研究现状与最新发展，通过对存在的问题分析，最后给出了有关的结论。     

用NILT导出的传输线瞬态分析模型

K Singhal与J Vlach的NILT(数值Laplace反变换) 技术是端接线性负载传输线分析的一种有效方法.本文利用这一NILT技术,导出了传输线的时域离散模型,由此可进行端接任意负载传输线的瞬态分析.这一模型毋须象通常的频域方法那样对传输线作有理逼近,因而不存在由此带来的数值问题,而计算量与它们相当.文中分别给出了均匀与非均匀传输线的处理,并用实例作了验证.     

VLSI Implementation of Forward Error Control Technique for ATM Networks

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.     

Optimal algorithms for adjacent side routing

We consider the switchbox routing problem of two-terminal nets in the case when all thek nets lie on two adjacent sides of the rectangle. Our routing model is the standard two-layer model. We develop an optimal algorithm that routes all the nets whenever a routing exists. The routing obtained uses the fewest possible number of vias. A more general version of this problem (adjacent staircase) is also optimally solved.This research was supported in part by NSA Contract No. MDA-904-85H-0015, NSF Grant No. DCR-86-00378, and by NSF Engineering Research Centers Program NSFD CDR 88003012.     

A VLSI architecture for a half-edge-based corner detector

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture for detection of corners in images. The corner detection technique is based on the half-edge concept and the first directional derivative of Gaussian. Apart from the location of the corner points, the algorithm also computes the corner orientation and the corner angle and outputs the edge map of the image. The symmetrical properties of the masks are utilized to reduce the number of convolutions effectively, from eight to two. Therefore, the number of multiplications required per pixel is reduced from 1800 to 392. Thus, the proposed architecture yields a speed-up factor of 4.6 over conventional convolution architectures. The architecture uses the principles of pipelining and parallelism and can be implemented in VLSI.     

深亚微米条件下的多层VLSI／MCM层分配的遗传算法

本文提出了一个深亚微米条件下的多层ＶＬＳＭＣＭ有约束分层层分配的遗传算法。该算法分为两步：首先进行超层分配，使各线网满足Ｃｒｏｓｓｔａｌｋ约束，且超层数目最少；然后进行各超层的通孔最少化二分层。与目前的层分配算法相比，该遗传算法具有目标全面，全局优化能力强等特点，是一种可应用于深亚微米条件下的ＩＣ ＣＡＤ的有效分层方法。     

Motion Perception Using Analog VLSI

Motion perception is arguably a fundamental mechanism used by natural species to accomplish a number of tasks, such as navigating freely in an unknown environment. Traditional motion perception methods tend to be computationally intensive, requiring powerful computers and large memories. However, by copying biological mechanisms, such as elementary motion discrimination at the early stages of the visual processing paths, it should be possible to build small and efficient motion perception systems. This paper describes the manner in which a simple motion perception model based on the insect visual system has been implemented using mixed analog/digital VLSI. The device has been fabricated in a 2 micron double metal, double polysilicon process, and comprises 61 photo-detectors, and associated analog and digital circuitry. While not entirely successful in that component mismatches hamper the detection of dark-to-bright changes in contrast, the results clearly show the feasibility of using such a device in autonomous control systems.