Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.     

虚拟嵌入式可编程控制器

本文介绍了虚拟嵌入式ＰＬＣ的原理并给出了一个实例。从某种意义上说，这种ＰＬＣ是一种思想方法。它适用于任何一种计算机系统。这种技术已成功运用于几个控制系统。     

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.     

Exact probabilistic testability measures for multi-output circuits

The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the X-gate, and applying to the resulting graph the analysis based on supergates.     

A Fully Differential Interface Circuit of Closed-loop Accelerometer with Force Feedback Linearization

In this paper,a fifth-order fully differential interface circuit（ IC） is presented to improve the noise performance for micromechanical sigma-delta（ Σ-Δ） accelerometer. A lead compensator is adopted to ensure the stability of the closed-loop high-order system. A low noise capacitance detection circuit is described with a correlated-double-sampling（ CDS） technique to decrease 1 /f noise and offset of the operational amplifier. This paper also proposes a self-test technique for the interface circuit to test the harmonic distortion. An electrostatic force feedback linearization circuit is presented to reduce the harmonic distortion resulting in larger dynamic range（ DR）. The layout of the IC is implemented in a standard 0. 6 μm CMOS technology and operates at a sampling frequency of 250 kHz. The interface consumes 20 mW from a 5 V supply. The post-simulation results indicate that the noise floor of the digital accelerometer is about- 140 dBV /Hz1 /2at low frequency. The sensitivity is 2. 5 V /g and the nonlinearity is 0. 11%. The self-test function is achieved with 98. 2 dB thirdorder harmonic distortion detection based on the electrostatic force feedback linearization.     

采用动态邻域扩展算法的非一致CA低功耗确定TPG

针对确定内建自测试向量发生器设计中常存在着对冗余向量依赖,导致测试应用时间增长,并产生额外的测试功耗等问题,提出一种新的低功耗确定测试向量发生器的综合算法.该向量发生器采用非一致细胞自动机的结构实现,利用基于模拟退火的动态邻域扩展算法寻找优化的细胞自动机的拓扑连接关系.对标准组合电路仿真实验的结果表明,所综合出的向量发生器可有效地产生给定的低功耗确定向量集,并且不影响原有的故障覆盖率和测试时间.     

Comments on “Aliasing Properties of Circular MISRs”

The analysis of aliasing probability presented in a recent article, Aliasing Properties of Circular MISRs [1], is based on an error model that cannot adequately represent real circuits. We show why conclusions presented in [1] should not be used in practice, substantiating our claim with experimental results.This work was supported in part by grants from the Natural Sciences and Engineering Research Council of Canada and in part by the British Columbia Advanced Systems Institute     

High level synthesis for loop-based BIST

Area and test time are two major overheads encountered during data path high level synthesis for BIST.This paper presents an approach to behavioral synthesis for loop-based BIST.y taking into account the requirements of the BIST scheme during behavioral synthesis processes,an area optimal BIST solution can be obtained.This approach is based on the use of test resources reusability that results in a fewer number of registers being modified to be test registers.This is achieved by incorporating self-testability constraints during register assignment operations.Experimental results on benchmarks are presented to demonstrate the effectiveness of the approach.     

内建自测试中多输入特征寄存器的硬件开销的减少

在内建自测试中,针对随机向量测试,本文提出了一种通过输出信号分组压缩来减少多输入特征寄存器MISR的硬件开销的方法。该方法是在分析输出信号之间相关性的基础上,根据给定的MISR阶数构造具有最小相关度的输出信号集合组,以此来减少输出信号分组压缩时的故障覆盖率损失。该方法不需附加任何辅助电路。