A Global Maximum Error Controller Based Nonlinearity Aware TPWL Method for Reducing Nonlinear Systems

Abstract

Model order reduction is a common practice to reduce large order systems so that their simulation and control become easy. Nonlinearity aware trajectory piecewise linear is a variation of trajectory piecewise linearization technique of order reduction that is used to reduce nonlinear systems. With this scheme, the reduced approximation of the system is generated by weighted sum of the linearized and reduced sub-models obtained at certain linearization points on the system trajectory. This scheme uses dynamically inspired weight assignment that makes the approximation nonlinearity aware. Just as weight assignment, the process of linearization points selection is also important for generating faithful approximations. This article uses a global maximum error controller based linearization points selection scheme according to which a state is chosen as a linearization point if the error between a current reduced model and the full order nonlinear system reaches a maximum value. A combination that not only selects linearization points based on an error controller but also assigns dynamic inspired weights is shown in this article. The proposed scheme generates approximations with higher accuracies. This is demonstrated by applying the proposed method to some benchmark nonlinear circuits including RC ladder network and inverter chain circuit and comparing the results with the conventional schemes.     

PSO优化多核RVM的模拟电路故障预测

针对模拟电路健康管理的特点，提出了一种基于PSO优化多核RVM的模拟电路故障预测方法。利用参数分析得到电路的输出频域响应作为特征，计算其与电路无故障标准响应的欧氏距离来表征电路元件健康值，将多个核函数线性组合，并用PSO优化多核RVM参数后的模型实现对各个时间点元件的健康值变化轨迹进行预测。仿真结果表明，该方法在小样本情况下，预测效果优于单一核函数的RVM模型，适用于健康管理中实时预测，具有较好的实用性。     

一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

Implementing Qubits with Superconducting Integrated Circuits

Superconducting qubits are solid state electrical circuits fabricated using techniques borrowed from conventional integrated circuits. They are based on the Josephson tunnel junction, the only non-dissipative, strongly non-linear circuit element available at low temperature. In contrast to microscopic entities such as spins or atoms, they tend to be well coupled to other circuits, which make them appealling from the point of view of readout and gate implementation. Very recently, new designs of superconducting qubits based on multi-junction circuits have solved the problem of isolation from unwanted extrinsic electromagnetic perturbations. We discuss in this review how qubit decoherence is affected by the intrinsic noise of the junction and what can be done to improve it. PACS: 03.67.-a, 03.65.Yz, 85.25.-j, 85.35.Gv     

Synchronous Full-Scan for Asynchronous Handshake Circuits

Handshake circuits form a special class of asynchronous circuits that has enabled the industrial exploitation of the asynchronous potential such as low power, low electromagnetic emission, and increased cryptographic security. In this paper we present a test solution for handshake circuits that brings synchronous test-quality to asynchronous circuits. We add a synchronous mode of operation to handshake circuits that allows full controllability and observability during test. This technique is demonstrated on some industrial examples and gives over 99% stuck-at fault coverage, using test-pattern generators developed for synchronous circuits. The paper describes how such a full-scan mode can be achieved, including an approach to minimize the number of dummy latches in case latches are used in the data path of the handshake circuit.     

BP算法的改进及用模拟电路实现的神经网络分类器

基于用模拟电路实现神经网络分类器的目的，对多层静态前馈神经网络的ＢＰ算法做了改进，采用线性限幅函数代替Ｓｉｇｍｏｉｄ函数作为神经元的激活函数，给出了改进的ＢＰ算法。对该算法性能的实验研究表明：这种改进算法不但方便了用线性模拟集成运算放大电路实现神经网络，而且具有学习速度快，映射能力强等优点。根据本文算法设计的神经网络分类器，无论是计算机仿真，还是模拟电路实现，都得到了比较高的识别率。     

A Symbolic Pole/Zero Extraction Methodology Based on Analysis of Circuit Time-Constants

This paper introduces a methodology for symbolic pole/zero extraction based on the formulation of the time-constant matrix of the circuits. This methodology incorporates approximation techniques specifically devoted to achieve an optimum trade-off between accuracy and complexity of the symbolic root expressions. The capability to efficiently handle even large circuits will be demonstrated through several practical circuits.     

一种语音混沌保密通信方案的研究与硬件实现

在硬件实验研究的基础上，建立一种环形蔡氏电路，提出用环蔡氏电路实现语音混沌保密通信的一种闭环逆系统方案，其特点是利用环形蔡氏电路的单向耦合原理，通过反馈的方法形成一个包括有用信号在内的极联闭合环路，从而实现改善端与接收端之间混沌系统的严格同步而不受有用信息调制的影响。理论分析与硬件实验结果证明，该方案同现有的其它混沌通信方案相比较，具有非线性失真小、保真度高的优点，完全能够满足传送语音信号的要求。