2.4GHz动态CMOS分频器的设计

对现阶段的主流高速CMOS分频器进行分析和比较,在此基础上设计一种采用TSPC(truesingle phase clock)和E-TSPC(extended TSPC)技术的前置双模分频器电路.该分频器大大提高了工作频率,采用0.6μm CMOS工艺参数进行仿真的结果表明,在5V电源电压下,最高频率达到3GHz,功耗仅为8mW.     

基于Delphi的报童模型的实现与动态仿真

已往库存论中的决策模型,它是把现实过程用数学的方法进行分析,得到决策值,但不能看到决策的过程,不能反映出现实生活中的不确定性、动态性。运用Delphi 7.0和SQL server 2000对销售过程进行了动态仿真,利用Newsboy模型的推广(S,s)订购策略来监控库存并做出决策,这样就体现出此过程的不确定性、动态性;且举出了一个仿真商品销售的实例,对其中的一些关键技术,如何仿真、算法的实现等进行了阐述。     

用SY87721实现城域网波分复用系统的多业务接入

为了使城域网的DWDM（密集波分复用）系统可以接入多种信号速率和格式，以满足用户的要求，首先介绍了一种波长转换板的设计方法，使用SY87721自适应提取28Mbit／s～2.7Gbit/s之间任意速率信号的时钟，其次介绍了SY87721提取时钟的工作原理、与单片机和CPLD（复杂可编程逻辑器件）的接口方式、对寄存器的配置和读出方式。最后介绍了使用参考时钟测量接入信号频率的方法，这会在系统维护时带来较大的方便。     

Modeling Effects of Rhythmic Context on Perceived Duration: A Comparison of Interval and Entrainment Approaches to Short-Interval Timing.

Relative merits of interval and entrainment conceptions of the internal clock were assessed within a common theoretical framework by 4 time-judgment experiments. The timing of tone onsets marking the beginning and ending of standard and comparison time intervals relative to a context rhythm were manipulated: onsets were on time, early, or late relative to the implied rhythm, and 2 distinct accuracy patterns emerged. A quadratic ending profile indicated best performance when the standard ended on time and worst performance when it was early or late, whereas a flat beginning profile (Experiments 1-3) indicated uniform performance for the 3 expectancy conditions. Only in Experiment 4, in which deviations from expected onset times were large, did significant effects of beginning times appear in time-discrimination thresholds and points of subjective equality. Findings are discussed in the context of theoretical assumptions about clock resetting, the representation of time, and independence of successive time intervals. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

一种用QuartusII实现的电子钟系统

对EDA技术的两种软件平台QuartusII和原有的MAX PlusII软件进行了比较，并利用QuartusII软件平台实现了电子钟系统的设计；该电子钟系统能精确计时并显示时间；有复位开关、设定开关和调整按钮可使系统复位及进行时间设定和调整。     

浅谈Small Cell应用前景及挑战

随着4G和智能设备的发展,未来移动通信数据量将成百倍增长。本文介绍了Smal Cel的基本概念,简要阐述其应用范围,并针对部署问题作了分析。     

基于门控时钟的低功耗时序电路设计新方法

为了实现更优化的时序电路低功耗设计,提出一种新的基于门控时钟技术的低功耗时序电路设计方法,设计步骤为:由状态转换表或状态转换图作出各触发器的行为转换表及行为卡诺图;根据实际情况对电路中的冗余时钟进行封锁,综合考虑门控时钟方案在系统功耗上的收益和代价,当门控代价过高时,对冗余的时钟实行部分封锁,得到各触发器的冗余抑制信号;将前一步骤中的保持项改为无关项,作出各触发器的次态卡诺图,得到激励函数;由冗余抑制信号和激励函数画出电路图,并检验电路能否自启动.以8421二-十进制代码同步十进制加法计数器和三位扭环形计数器作为设计实例,经Hspice模拟与能耗分析证明,采用该方法设计的电路具有正确的逻辑功能,并能有效降低电路功耗,与已有方法设计的电路相比,能够节省更多的功耗或者提升电路性能.     

Ad hoc网络时钟同步研究*

为解决时钟同步方案存在依赖特殊节点以及算法精度不高等问题,在组网过程与自组网互同步相结合的基础上,完成网络节点的时钟同步,并通过测量网络延迟以提高同步精度.方案在一跳场景下验证,可将误差维持在15μs左右,提高了同步精度,并且本方案不需要特殊节点,各个节点只需要收到一个同步帧就可以自发地调整时钟,同步帧的开销小、实现简单,适用于多跳和灵活易变的Ad hoc网络.     

A High-Precision Time Handling Library

An appropriate assessment of end-to-end network performance presumes highly efficient time tracking and measurement with precise time control of the stopping and resuming of program operation. In this paper, a novel approach to solving the problems of highly efficient and precise time measurements on PC-platforms and on ARM-architectures is proposed. A new unified High Performance Timer and a corresponding software library offer a unified interface to the known time counters and automatically identify the fastest and most reliable time source, available in the user space of a computing system. The research is focused on developing an approach of unified time acquisition from the PC hardware and accordingly substituting the common way of getting the time value through Linux system calls. The presented approach provides a much faster means of obtaining the time values with a nanosecond precision than by using conventional means. Moreover, it is capable of handling the sequential time value, precise sleep functions and process resuming. This ability means the reduction of wasting computer resources during the execution of a sleeping process from 100% （busy-wait） to 1-1.5%, whereas the benefits of very accurate process resuming times on long waits are maintained.     

A single layer zero skew clock routing in X architecture

With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture (called Planar-CRX). Our Planar-CRX method integrates the extended deferred-merge embedding algorithm (DME-X, which extends the DME algorithm to X architecture) with modified Ohtsuki’s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm. Supported in part by the National Natural Science Foundation of China (Grant No. 60876026), and the Specialized Research Fund for the Doctoral Program of Higher Education (Crant No. 200800030026)