Features of a Scan and Clock Resource chip for providing access to board-level test functions

The architecture and some of the specific features of a Scan and Clock Resource (SCR) chip are described. This chip is currently being used in a high-end workstation product to provide access to the testability features of the individual chips and/or printed circuit boards. Using a board-level controller to gain access to the testability features of system components and interfacing the controller to a diagnostics processor (or external tester) is emerging as a common strategy for designing testable digital systems. Based upon experience gained from such an application, controller features that are deemed useful are discussed.This paper is an enhanced version of the author's earlier paper titled Towards a Standard Approach for Controlling Board-Level Test Functions, presented at the IEEE International Test Conference, ITC'90, Washington D.C., September 1990.     

Fundamentals of MCM Testing and Design-for-Testability

Products motivated by performance-driven and/or density-driven goals often use Multi-Chip Module (MCM) technology, even though it still faces several challenging problems that need to be resolvedbefore it becomes a widely adopted technology. Among its mostchallenging problems is achieving acceptable MCM assembly yieldswhile meeting quality requirements. This problem can be significantlyreduced by adopting adequate MCM test strategies: to guarantee thequality of incoming bare (unpackaged) dies prior to module assembly;to ensure the structural integrity and performance of assembled modules; and to help isolate the defective parts and apply the repair process.This paper describes todays MCM test problems and presents thecorresponding test and design-for-testability (DFT) strategies usedfor bare dies, substrates, and assembled MCMs.     

基于混沌多目标粒子群算法的测点优选方法

模拟电路的测点优选问题旨在寻找总测试代价最低、测试性能最好的测点集合。之前的研究通常把最高测试性能作为约束条件,以单目标优化思想搜索代价最小的测点集合。而实际应用中,对测点集合的需求是多样化的,需要根据实际需求调整性能和代价间的关系。提出了混沌多目标粒子群算法,该算法采用多目标优化思想,能同时找到多样化的方案,并根据多目标优化问题的特点,加入了混沌机制提高算法的搜索能力。实验结果表明,该算法能找到对应不同测试性能的最优测点集合,与其他算法相比,算法成功率最高、找到的方案最多且运行速度较快。对模拟电路的可测性设计和故障诊断很有帮助。     

混合技术PCB可测试性设计优化方法

文中对既包含了ＪＴＡＧ芯片又包含非ＪＴＡＧ芯片的混合技术电路板的设计问题进行了深入的研究,构造了两种优化设计算法,应用这两种算法的设计的电路,不仅可以满足应用ＪＴＡＧ机制对所有芯片进行测试的要求－可测试必要条件,而且具备最低的整体费用。文中给出了具体的算法,并用实例对算法进行了说明。     

航空设备的测试性设计和验证技术概述

介绍了航空设备的测试性、测试性设计、测试性验证评估等,分析提出了国内航空设备测试性设计与验证技术现状以及存在问题的技术原因.     

Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach

In this paper a concept is proposed to combine a bus-transfer based test approach (AMBA) with the well-known scan-test technique. This novel approach combines the advantages of modularity and core reuse (AMBA) with the benefits of high fault coverages and short time-to-market cycles (scan). The consequences with respect to test hardware implementation and tool flow are discussed.     

Designing “Dual Personality” IEEE 1149.1 Compliant Multi-Chip Modules

The IEEE 1149.1 Test Access Port and Boundary-Scan ArchitectureStandard can be used at many different levels in the integration hierarchy of a product. However there is one level where using the standard poses some difficulty. Multi-Chip Modules (MCM) belong to this level. This paper explores the problemand proposes a set of solutions for various classes of MCMs.     

A Novel RF Test Scheme Based on a DFT Method

This paper presents a new RF testing scheme based on a design-for-testability (DFT) method for measuring functional specifications of RF integrated circuits (IC). The proposed method provides the input impedance, gain, noise figure, voltage standing wave ratio (VSWR) and output signal-to-noise ratio (SNR) of a low noise amplifier (LNA). The RF test scheme is based on theoretical expressions that produce the actual RF device specifications by utilizing the output DC voltages from the DFT chip. This technique can save marginally failing chips in production testing as well as in the system, hence saving a tremendous amount of revenue from unnecessary device replacements.     

DSP数据通路基于累加器测试的结构可测性设计

在综述VLSI结构可测性设计方法的基础上,提出了DSP数据通路基于累加器测试的结构可测性设计方案:利用选择器或三态门实现电路测试、工作模式的切换;在测试模式时,电路中的寄存器复用为扫描链以完成测试矢量的传送从而提高电路的可测试性能.基于本方案的FFT处理器、IIR滤波器、DF-FPDLMS自适应滤波器的数据通路的可测性设计,若忽略数据线延迟,其关键路径仅比原来的分别增加了1、2、0倍的选择器或三态门门延迟.实验表明,若字宽、阶数均为8,它们所需额外硬件开销分别为原来的5.416%、4.969%、4.783%,关键路径分别增加了1.839%、2.382%、0.036%.结果表明,该方案通用性好,扩展性强,额外硬件开销小,几乎不会影响原电路的性能.     

一种混合信号测试系统的设计及实现

针对一款混合信号的视频编解码芯片的参数测试要求,依据电路内部的测试结构,设计了一个基于纯数字自动测试设备（ATE）的混合信号电路测试系统。该测试系统通过增加MCU、ADC、DAC、FIFO、运放、可控开关等外围电路实现对芯片参数的测试。详细阐述了测试系统的总体方案、硬件设计和软件设计。通过软件和硬件的协同工作,该测试系统能够对含有AD、DA模块的混合信号电路相关参数进行测试,实现电路整体性能的评估。该测试系统原理清晰,结构简单,扩展灵活、方便。