From defects creation to circuit reliability - A bottom-up approach (invited)

This paper presents a theoretical framework about interface states creation rate from Si-H bonds at the Si/SiO₂ interface. It includes three mains ways of bond breaking. In the first case, the bond can be broken thanks to the bond ground state rising with an electrical field. In the two others cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows us physically modeling the reliability of MOSFET transistors, and particularly NBTI permanent part, and Channel Hot Carrier (CHC) to Cold Carrier (CCC) damage. Finally, the translation of these physical models into reliability spice models is discussed. These models pave the way to Design-in Reliability (DiR) approach which seeks to provide a quantitative assessment of reliability - CMOS device reliability in this case - at design stage thereby enabling judicious margins to be taken beforehand.     

超深亚微米IC设计中的天线效应

本文主要分析了超深亚微米集成电路设计中天线效应产生机理及其消除方法,同时还给出了天线比率的具体计算方法。将这些方法应用于雷达信号处理SOC芯片后端设计中,解决了设计中存在的天线效应问题,保证了一次流片成功。     

叠栅MOSFETs的结构设计与研究

通过分析设计,提出了一种新型结构的叠栅MOSFET,它的栅电容是由两个电容混联组成,所以它有较小的栅电容和显著的抑制短沟道效应的作用。模拟软件MEDICI仿真结果验证了理论分析的预言,从而表明该结构可用作射频领域。     

用于PDP扫描驱动的双高压p-LDMOS及其兼容工艺

报道了基于硅外延BCD工艺的高栅源、高漏源电压的功率pMOS的设计.采用1μm厚的场氧化层作为栅氧介质及RESURF原理优化的漏极漂移区,器件面积为80μm×80μm,工艺上简化为18次光刻,兼容标准CMOS、双极管和高压VDMOS. 测试管耐压超过200V,集成于64路170V PDP扫描驱动芯片,通过了上机测试.     

用于PDP扫描驱动的双高压p-LDMOS及其兼容工艺

报道了基于硅外延BCD工艺的高栅源、高漏源电压的功率pMOS的设计.采用1μm厚的场氧化层作为栅氧介质及RESURF原理优化的漏极漂移区,器件面积为80μm×80μm,工艺上简化为18次光刻,兼容标准CMOS、双极管和高压VDMOS.测试管耐压超过200V,集成于64路170V PDP扫描驱动芯片,通过了上机测试.