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1.
采用直流磁控溅射和后退火氧化工艺在p型GaAs单晶衬底上成功制备了n-VO_2/pGaAs异质结,研究了不同退火温度和退火时间对VO_2/GaAs异质结性能的影响,并分析其结晶取向、化学组分、膜层质量以及光电特性。结果表明,在退火时间2 h和退火温度693 K下能得到相变性能最佳的VO_2薄膜,相变前后电阻变化约2个数量级。VO_2/GaAs异质结在308 K、318 K和328 K温度下具有较好的整流特性,对应温度下的阈值跳变电压分别为6.9 V、6.6 V和6.2 V,该结果为基于VO_2相变特性的异质结光电器件的设计与应用提供了可行性。 相似文献
2.
《Advanced Powder Technology》2022,33(11):103777
In this study the constructional modification of Graphitic carbon nitride nanosheet (GCN-ns) has been made with the aid of ZnCr layered double hydroxide (ZC-LDH) in a unique 2D-2D structure to enhance its visible light absorption. Optical and morphological study presents successful incorporation of ZC-LDH on the surface of GCN-ns. Through adjusting of GCN-ns by ZC-LDH lower recombination rate of e?/h+ pairs, longer lifetimes and an increase in contamination reduction was brought out. The binary nanocomposite was employed to effectively degrade Rhodamine B under UV/vis light irradiation. The improvement in photocatalytic abilities was proven to be related to in situ self-production of H2O2 on GCN-ns/ZC-LDH surface by Xe light irradiation which in return accounts for additional hydroxide radical generation. Radical quenching experiments specified the main active species involved while the consequent step-scheme (S-scheme) charge transfer mechanism was proposed. 相似文献
3.
《International Journal of Hydrogen Energy》2022,47(52):22165-22179
Aluminum alloy bipolar plates have unique application potential in proton exchange membrane fuel cell (PEMFC) due to the characteristics of lightweight and low cost. However, extreme susceptibility to corrosion in PEMFC operation condition limits the application. To promote the corrosion resistance of aluminum alloy bipolar plates, a Ni–P/TiNO coating was prepared by electroless plating and closed field unbalanced magnetron sputter ion plating (CFUMSIP) technology on the 6061 Al substrate. The research results show that Ni–P interlayer improves the deposition effect of TiNO outer layer and increase the content of TiN and TiOxNy phases. Compared to Ni–P and TiNO single-layer coatings, the Ni–P/TiNO coating samples exhibited the lowest current density value of (1.10 ± 0.02) × 10?6 A·cm?2 in simulated PEMFC cathode environment. Additionally, potential cyclic polarization measurements were carried out aiming to evaluate the durability of the aluminum alloy bipolar plate during the PEMFC start-up/shut-up process. The results illustrate that the Ni–P/TiNO coating samples exhibit excellent stability and corrosion resistance. 相似文献
4.
We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation (10000 randomizations). With this simulation, we could study the effects of varying the dimensions (length and width), and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region (off) and overthreshold (on). It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion (compared with that of the subthreshold). These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel. 相似文献
5.
For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (Ron,sp) of 2 mΩ cm2, which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively. 相似文献
6.
Aiming to environment protection, green solvents are crucial for commercialization of solution-processed optoelectronic devices. In this work, d-limonene, a natural product, was introduced as the non-aromatic and non-chlorinated solvent for processing of polymer light-emitting diodes (PLEDs) and organic field effect transistors (OFETs). It was found that d-limonene could be a good solvent for a blue-emitting polyfluorene-based random copolymer for PLEDs and an alternating copolymer FBT-Th4(1,4) with high hole mobility (μh) for OFETs. In comparisons to routine solvent-casted films of the two conjugated polymers, the resulting d-limonene-deposited films could show comparable film qualities, based on UV–vis absorption spectra and observations by atomic force microscopy (AFM). With d-limonene as the processing solvent, efficient blue PLEDs with CIE coordinates of (0.16, 0.16), maximum external quantum efficiency of 3.57%, and luminous efficiency of 3.66 cd/A, and OFETs with outstanding μh of 1.06 cm2 (V s)−1 were demonstrated. Our results suggest that d-limonene would be a promising non-aromatic and non-chlorinated solvent for solution processing of conjugated polymers and molecules for optoelectronic device applications. 相似文献
7.
8.
Youngseok Lee Cheolmin Park Nagarajan Balaji Youn-Jung Lee Vinh Ai Dao 《Israel journal of chemistry》2015,55(10):1050-1063
Over the past few decades, crystalline silicon solar cells have been extensively studied due to their high efficiency, high reliability, and low cost. In addition, these types of cells lead the industry and account for more than half of the market. For the foreseeable future, Si will still be a critical material for photovoltaic devices in the solar cell industry. In this paper, we discuss key issues, cell concepts, and the status of recent high-efficiency crystalline silicon solar cells. 相似文献
9.
1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm2 is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm2 array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall Vmin of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances. 相似文献
10.