16信道0.35μmCMOS/VCSEL光发射模块

研究了垂直腔面发射激光器 (VCSEL)及其列阵器件的光谱特性、调制特性、高频特性及与微电子电路的兼容性 ,将 1× 16的VCSEL与CMOS专用集成电路进行多芯片组装 (MCM ) ,混合集成为 16信道VCSEL光发射功能模块 .测试过程中 ,功能模块的光电特性及其均匀性良好 ,测量的 - 3dB频带宽度大于 2GHz.     

Characterization and optimization of copper chemical mechanical planarization

The feature scale planarization of the copper chemical mechanical planarization (CMP) process has been characterized for two copper processes using Hitachi 430-TU/Hitachi T605 and Cabot 5001/Arch Cu10K consumables. The first process is an example of an abrasive-free polish with a high-selectivity barrier slurry, while the second is an example of a conventional abrasive slurry with a low-selectivity barrier slurry. Copper fill planarization has been characterized for structures with conformal deposition as well as with bumps resulting from bottom-up fill. Dishing and erosion were characterized for several structures after clearing. The abrasive-free polish resulted in low sensitivity to overpolish and low saturation levels for dishing and erosion. Consequently, this demonstrated superior performance when compared to the International Technology Roadmap for Semiconductors (ITRS) 2000 roadmap targets for planarization. While the conventional slurry could achieve the 0.13-μm technology node requirements, the abrasive-free polish met the planarization requirements beyond the 0.10-μm technology node.     

光互连技术的研究现状及发展

本文首先总结了光学互连的主要实现途径，然后评述了光互连的研究现状与最新发展，通过对存在的问题分析，最后给出了有关的结论。     

用NILT导出的传输线瞬态分析模型

K Singhal与J Vlach的NILT(数值Laplace反变换) 技术是端接线性负载传输线分析的一种有效方法.本文利用这一NILT技术,导出了传输线的时域离散模型,由此可进行端接任意负载传输线的瞬态分析.这一模型毋须象通常的频域方法那样对传输线作有理逼近,因而不存在由此带来的数值问题,而计算量与它们相当.文中分别给出了均匀与非均匀传输线的处理,并用实例作了验证.     

A new precipitate phase in Al-4wt. % Cu thin-film interconnects

We report here the identification of a new precipitate phase in thin-film Al-4wt.%Cu metallization used for interconnects on integrated circuits. The phase is based on a trigonal distortion of a face centered cubic lattice. Computer simulation of electron diffraction intensities suggests that the basis structure is isomorphous with Al₂Ca but with a large and ordered population of vacancies on Cu sites. The reason for the formation of the new phase and its implications for electromigration reliability are discussed.     

一个用于VHSIC连接线瞬态分析的电路模拟器

本文介绍了一个可对含连接线的电路进行瞬态分析的电路模拟器,该模拟器是在SPICE基础上经修改扩充而成的,连接线的处理采用了文献[1]的方法.文中介绍了方法的基本原理,讨论了数值Laplace反变换时参数的选择与误差的控制.实际VHSIC电路的试算结果表明,该模拟器是相当有效的.     

Xilinx XC4000系列FPGA自动测试平台搭建

随着FPGA的发展,FPGA测试技术也得到了相应的发展。因为FPGA的结构和传统专用集成电路(ASIC)有着本质的区别,在FPGA中不能形成可测性设计电路,但它的可编程能力决定了其测试电路可以通过编程的方法来实现。本文讨论了Xilinx XC4000系列FPGA中CLB资源和互连资源的自动测试方法。而且提出了一种新的测试资源坐标定位方法,使得由软件仿真向器件真实测试取得了突破。并搭建了硬件测试平台。     

Evaluating the energy consumption and the silicon area of on-chip interconnect architectures

Sophisticated on-chip interconnects using packet and circuit switching techniques were recently proposed as a solution to non-scalable shared-bus schemes currently used in Systems-on-Chip (SoCs) implementation. Different interconnect architectures have been studied and adapted for SoCs to achieve high throughput, low latency and energy consumption, and efficient silicon area. Recently, a new on-chip interconnect architecture by adapting the WK-recursive network topology structure has been introduced for SoCs. This paper analyses and compares the energy consumption and the area requirements of Wk-recursive network with five common on-chip interconnects, 2D Mesh, Ring, Spidergon, Fat-Tree and Butterfly Fat-Tree. We investigated the effects of load and traffic models and the obtained results show that the traffic models and load that ends processing elements has a direct effect on the energy consumption and area requirements. In these results, WK-recursive interconnect generally has a higher energy consumption and silicon area requirements in heavy traffic load.     

Performance evaluation of directory protocols on an optical broadcast-based distributed shared memory multiprocessor

Recent advances in the development of optical technologies suggest the possible emergence of broadcast-based optical interconnects within cache-coherent distributed shared memory (DSM) multiprocessor architectures. It is well known that the cache-coherence protocol is a critical issue in designing such architectures because it directly affects memory latencies. In this paper, we evaluate via simulation the performance of three directory-based cache-coherence protocols; strict request-response, intervention forwarding and reply forwarding on the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus), which is a low-latency and high-bandwidth broadcast-based fiber-optic interconnection network supporting DSM. The simulated system contains 64 nodes, each of which has a processor, a cache controller, a directory controller and an output channel. Simulations have been conducted for each protocol to measure average processor utilization, average network latency and average number of packets transferred over the network for varying values of the important DSM parameters such as the ratio of the mean channel service time to mean thread run time (T/R), probability of a cache block being in modified state {P(M)}, the fraction of write misses {P(W)} and home node contention rate. The results reveal that for all cases, except for low values of P(M), intervention forwarding gives the worst performance (lowest processor utilization and highest latency). The performance of strict request-response and reply forwarding is comparable for several values of the DSM parameters and contention rate. For a contention rate of 0%, the increase of P(M) makes reply forwarding perform better than strict request-response. The performance of all protocols decreases with the increase of P(W) and contention rate. However, the performance of strict request-response is the least affected among other protocols due to the negative impact of the increase of P(W) and contention rate. Therefore, for the full contention case (i.e. contention rate of 100%); for low values of P(M), or for mid values of P(M) and high values of P(W), strict request-response performs better than reply forwarding. These results are significant in the sense that they provide an insight to multiprocessor architecture designers for comparing the performance of different directory-based cache-coherence protocols on a broadcast-based interconnection network for different values of the DSM parameters and varying rates of contention.     

Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits

A concept for a future integer arithmetic unit suitable for a realization with 3-D optoelectronic very large scale integrated (VLSI) circuits is presented. Due to the use of optical interconnections running vertically to the circuit's surface no pin limitation is given. This allows massively parallelism and a higher throughput performance than in all-electronic solutions. To exploit the potential of optical interconnections in VLSI systems efficiently well-adapted low-level algorithms and architectures have to be developed. This is demonstrated for a pipelined arithmetic unit using a redundant number representation. A transistor layout for the optoelectronic circuits is given as well as a specification for the necessary optical interconnection scheme linking the circuits with free-space optics. It is shown that the throughput can be increased by a factor of 10 to 50 compared to current all-electronic processors by considering state-of-the-art optical and optoelectronic technology. Furthermore we present results we gained by investigations on a first realized optoelectronic VLSI test chip.