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1.
孙咸 《焊管》2022,45(5):22-35
综述了铁素体与铁素体异种金属焊缝(dissimilar metal welds,DMWs)接头界面组织及其影响。结果表明,在焊后热处理或运行温度下的铁素体钢DMWs接头的不均匀界面组织中,通常会形成脱碳层和增碳层。在铁素体钢DMWs焊接接头界面组织影响因素中,焊缝金属的化学成分有重要影响;焊后热处理规范(温度和时间)、工作温度下运行时间的影响较为突出;焊接工艺参数的影响亦不可忽略。异种钢接头界面处近缝区裂纹的产生,以及接头的蠕变强度随Larson Miller 参数增大而下降等不利影响,均为异种钢界面碳迁移行为所导致。焊缝成分控制法是接头界面组织控制或改善的必要条件,而脱碳层部位转移法能有效防止裂纹发生,亦是接头安全运行的重要工艺措施之一。  相似文献   
2.
Large‐scale production of hydrogen from water‐alkali electrolyzers is impeded by the sluggish kinetics of hydrogen evolution reaction (HER) electrocatalysts. The hybridization of an acid‐active HER catalyst with a cocatalyst at the nanoscale helps boost HER kinetics in alkaline media. Here, it is demonstrated that 1T–MoS2 nanosheet edges (instead of basal planes) decorated by metal hydroxides form highly active edge 1T‐MoS 2 / edge Ni ( OH ) 2 heterostructures, which significantly enhance HER performance in alkaline media. Featured with rich edge 1T‐MoS 2 / edge Ni ( OH ) 2 sites, the fabricated 1T–MoS2 QS/Ni(OH)2 hybrid (quantum sized 1T–MoS2 sheets decorated with Ni(OH)2 via interface engineering) only requires overpotentials of 57 and 112 mV to drive HER current densities of 10 and 100 mA cm?2, respectively, and has a low Tafel slope of 30 mV dec?1 in 1 m KOH. So far, this is the best performance for MoS2‐based electrocatalysts and the 1T–MoS2 QS/Ni(OH)2 hybrid is among the best‐performing non‐Pt alkaline HER electrocatalysts known. The HER process is durable for 100 h at current densities up to 500 mA cm?2. This work not only provides an active, cost‐effective, and robust alkaline HER electrocatalyst, but also demonstrates a design strategy for preparing high‐performance catalysts based on edge‐rich 2D quantum sheets for other catalytic reactions.  相似文献   
3.
Abstract

Model order reduction is a common practice to reduce large order systems so that their simulation and control become easy. Nonlinearity aware trajectory piecewise linear is a variation of trajectory piecewise linearization technique of order reduction that is used to reduce nonlinear systems. With this scheme, the reduced approximation of the system is generated by weighted sum of the linearized and reduced sub-models obtained at certain linearization points on the system trajectory. This scheme uses dynamically inspired weight assignment that makes the approximation nonlinearity aware. Just as weight assignment, the process of linearization points selection is also important for generating faithful approximations. This article uses a global maximum error controller based linearization points selection scheme according to which a state is chosen as a linearization point if the error between a current reduced model and the full order nonlinear system reaches a maximum value. A combination that not only selects linearization points based on an error controller but also assigns dynamic inspired weights is shown in this article. The proposed scheme generates approximations with higher accuracies. This is demonstrated by applying the proposed method to some benchmark nonlinear circuits including RC ladder network and inverter chain circuit and comparing the results with the conventional schemes.  相似文献   
4.
针对模拟电路健康管理的特点,提出了一种基于PSO优化多核RVM的模拟电路故障预测方法。利用参数分析得到电路的输出频域响应作为特征,计算其与电路无故障标准响应的欧氏距离来表征电路元件健康值,将多个核函数线性组合,并用PSO优化多核RVM参数后的模型实现对各个时间点元件的健康值变化轨迹进行预测。仿真结果表明,该方法在小样本情况下,预测效果优于单一核函数的RVM模型,适用于健康管理中实时预测,具有较好的实用性。  相似文献   
5.
6.
xBi2/3Cu3Ti4O12/(1-x)CaCu3Ti4O12 composites were prepared by traditional solid-state reaction method. Extremely high nonlinear coefficient of 25 and breakdown field of 18.92 kV·cm−1 were obtained in small current range of 0.1−1 mA·cm-2. In addition, reduced dielectric loss of 0.055 was achieved with high dielectric constant of 1369. Optimized nonlinear and dielectric properties were integrated to make the composites a promising dual-function varistor-capacitor candidate. Microstructure analysis discovered two areas with various Bi/Ca ratio, designated as Bi-H and Bi-L respectively. It was found that the maximum ratio of Bi-H/Bi-L heterogeneous interface corresponded to optimized nonlinear and dielectric performance, which was associated with elevated potential barrier height and huge grain boundary resistance. Combined with relaxation analysis, a core-shell structure was proposed to elaborate microstructure evolution in xBi2/3Cu3Ti4O12/(1-x)CaCu3Ti4O12 composite. According to the core-shell model, variation of heterogeneous interface was illustrated on how to influence nonlinear properties, which was well fitted to experimental results.  相似文献   
7.
8.
曾秋云 《电子科技》2015,28(4):116-119
基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。  相似文献   
9.
Separation membranes with higher molecular weight cut-offs are needed to separate ions and small molecules from a mixed feed. The molecular sieving phenomenon can be utilized to separate smaller species with well-defined dimensions from a mixture. Here, the formation of freestanding polyimine nanofilms with thicknesses down to ≈14 nm synthesized via self-assembly of pre-synthesized imine oligomers is reported. Nanofilms are fabricated at the water–xylene interface followed by reversible condensation of polymerization according to the Pieranski theory. Polyimine nanofilm composite membranes are made via transferring the freestanding nanofilm onto ultrafiltration supports. High water permeance of 49.5 L m-2 h−1 bar−1 is achieved with a complete rejection of brilliant blue-R (BBR; molecular weight = 825 g mol−1) and no more than 10% rejection of monovalent and divalent salts. However, for a mixed feed of BBR dye and monovalent salt, the salt rejection is increased to ≈18%. Membranes are also capable of separating small dyes (e.g., methyl orange; MO; molecular weight = 327 g mol−1) from a mixed feed of BBR and MO. Considering a thickness of ≈14 nm and its separation efficiency, the present membrane has significance in separation processes.  相似文献   
10.
《Microelectronics Journal》2015,46(11):1012-1019
This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm2 and 0.08 mm2, respectively.  相似文献   
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