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提出了一种用于片上全局互连的混合插入方法. 该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点,将它们混合插入到连线的合适位置,从而降低互连的延时和功耗. 模拟结果表明,该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善. 相似文献
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基于互连的一种FPGA最优功耗延时积设计 总被引:1,自引:1,他引:0
为了有效地解决困扰现场可编程门阵列发展的功耗延时积问题,采用集成电路互连的分段式结构和低压摆电路,提出了一种基于互连的最优功耗延时积现场可编程门阵列设计方法. 对于产生传输线效应的现场可编程门阵列互连,通过优化互连的段数,在互连最外面的输入端和输出端分别连接低压摆电路的驱动部分和接收部分,在内部的每段互连之间插入最优尺寸的缓冲部分. 理论与模拟表明,用这种方法设计的现场可编程门阵列能使功耗延时积减小近一个数量级,同时较好地保持现场可编程门阵列的面积性能. 相似文献
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In order to achieve a high-speed low-power NoC(Network-on-chip) clock network, considering the Mesh NoC, a waterfall clock network based on the capacitively-driven low-swing transceiver in which we replace traditional MOS capacitance by metal-insulator-metal(MIM) capacitance as the driven capacitance and receiver coupling capacitance is proposed. These structures are simulated by 0.13μm CMOS technology with Spectre simulators. Results show that the proposed clock network can reach a high frequency up to 5GHz,compared with traditional networks, and this network allows up to 49% power saving and 55% delay reduction. At the same time, this network has a better noise suppression ability. 相似文献
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在高性能的片上系统设计中,功耗已经成为制约片上网络发展的重要约束。首先用混合插入方法计算了全局芯片网络中各条路径的延时和功耗。相比起用最优中继驱动器插入方法,这种情况下互连线的延时和功耗分别降低了24.36%和11.81%。在混合插入方法的基础上进行优化后,相比起用混合插入方法,互连线功耗降低了21.75%。 相似文献
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A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs. 相似文献
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