Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM

Single event multiple-cell upsets (MCU) increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.     

Design of a soft-error robust microprocessor

The costs to protect a commercial microprocessor against soft errors are discussed in this work. Based on hardware and time redundancies, a protection scheme was designed at RT level to mitigate transient faults on combinational and memory circuits. A fault-tolerant IC version of a mass-produced 8-bit microprocessor is protected by the scheme. Design issues and results in area, performance and power are presented comparing the robust microprocessor with its non-protected version. The costs by flip-flop are also discussed permitting to estimate the overheads in area for any architecture. Furthermore, the RT-level protection scheme is compared with an electrical-level scheme based on a non-standard gate.     

Simulating Single Event Transients in VDSM ICs for Ground Level Radiation

This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach.     

基于SRAM型FPGA的容错性设计

随着SRAM型FPGA在航天领域中的不断应用,空间环境下单粒子翻转（single event upsets,SEU）问题不断涌现。为了加强航天电子产品在轨的可靠性与安全性,介绍了一种基于Xilinx公司Vertix-II系列FPGA的容错性设计,该设计深入研究了动态刷新（Scrubbing）原理,利用反熔丝型FPGA作为控制器实现了对SRAM型FPGA的配置数据进行ms级的周期刷新,并对2种FPGA加入了三模冗余（triple modular redundancy,TMR）及回读比较重加载方法,设计兼顾了系统重构、冗余处理和故障恢复,效果良好。实验结果表明刷新周期仅为131.2ms,远大于空间单粒子翻转率,能有效地抑制单粒子翻转效应的影响。     

65 nm双阱CMOS静态随机存储器多位翻转微束及宽束实验研究

利用微束和宽束辐照装置分别对两款65 nm双阱CMOS静态随机存储器(SRAM)进行重离子垂直辐照实验,将多位翻转（multiple-cell upset, MCU）类型、位置、事件数与器件结构布局相结合对单粒子翻转（single-event upset, SEU）的截面、MCU机理进行深入分析。结果表明,微束束斑小且均匀性好,不存在离子入射外围电路的情况;NMOS晶体管引发的MCU与总SEU事件比值高达32%,NMOS晶体管间的电荷共享不可忽略;实验未测得PMOS晶体管引发的MCU,高密度阱接触能有效抑制PMOS晶体管间的电荷共享;减小晶体管漏极与N阱/P阱界面的间距能降低SRAM器件SEU发生概率;减小存储单元内同类晶体管漏极间距、增大存储单元间同类晶体管漏极间距,可减弱电荷共享,从而减小SRAM器件MCU发生概率。     

基于FPGA定时刷新控制单元的应用技术研究

SRAM型FPGA在航天领域有着广泛的应用,为解决FPGA在宇宙环境中单粒子翻转的问题,适应空间应用需求,给出了一种低成本抗辐照解决方案,对耐辐射FPGA器件进行抗单粒子翻转加固设计。该方案兼容多种型号FPGA芯片,从3片SPI FLASH中读取配置数据,通过串行接口配置FPGA,并在配置完成后按照设定时间周期性刷新芯片,可以满足航天领域对抗辐照型FPGA的使用需求。     

CuxSiyO阻变存储器单粒子和总剂量辐照效应

对CuxSiyO结构的阻变存储器(RRAM)进行了总剂量(TID)以及单粒子辐照(SEE)实验.总剂量实验中,1T1R样品分别接受总剂量为1,2和3 kGy (SiO2)的60Co γ射线辐射.样品中没有出现低阻在辐照后翻转的现象.单粒子辐照实验中,16 kbit RRAM阵列样品分别接受线性能量转移(LET)值最高达75 MeV的4种离子束的辐射.样品中没有出现低阻在辐照后翻转的现象.除一组无翻转外,存储单元的高阻到低阻的翻转率皆在0.06％左右.实验结果证实了RRAM中已经形成的导电通道不会受辐照影响,因此不存在低阻翻转为高阻的现象.     

适用于空间环境下的FPGA容错与重构体系

FPGA极大地提高了电子系统设计的灵活性和通用性，被广泛地应用在各个领域。在空间环境中，FPGA 容易受到SEU的影响而导致内部逻辑的紊乱，系统重构与故障恢复也比较困难。该文提出了一种在星载环境下，使用CPLD对FPGA进行基于错误诊断的容错体系结构设计，兼顾到了系统重构与故障恢复，在实验中取得了较好的效果。     

A feedforward excess-phase cancellation technique for integrators

Integrators are useful analogue function blocks. A representative application of integrators is a continuous-time filter on an integrated circuit. Excess phase shift of integrators is one of the most severe problems, because excess phase shift at the unity gain frequency degrades the frequency characteristics of the filters. This paper describes a feedforward excess-phase cancellation technique. The proposed technique is applied to integrators which have feedback with an amplifier. The proposed idea is verified by experiment. It is shown that the excess-phase shift due to the gain-bandwidth product of operational amplifiers is cancelled. The proposed technique is useful for realization of integrated continuous-time filters using integrators because extra capacitors are unnecessary. An integrator with the excess-phase cancellation and a third-order leapfrog filter using the integrator are designed and demonstrated by HSPICE simulation. The integrator has a parasitic pole whose frequency is proportional to the unity gain frequency. The simulation results show that the phase characteristics are improved by the proposed technique over the wide range of the unity gain frequency.     

SRAM-FPGA抗单粒子翻转方法和预估

为解决卫星通信系统中赛灵思公司的静态随机存储器型现场可编程门阵列(Xilinx SRAMFPGA)单粒子翻转问题,提出了一种占用硬件资源少,可靠度高的抗单粒子方法．该方法使用爱特公司的现场可编程门阵列作为检测芯片,可编程只读存储器芯片存储屏蔽位文件,通过联合测试工作组模式回读Xilinx FPGA配置文件并进行校验,发现出错则重新加载配置文件,消除单粒子翻转影响．该方法已成功在轨应用于某卫星通信系统．为计算卫星通信系统的可靠度,提出使用品质因数方法预估静态随机存储器型现场可编程门阵列单粒子翻转率,并与在轨实测数据进行比较,证明使用该方法的正确性,同时计算出实际飞行轨道的单粒子翻转率系数,为其他静态随机存储器型现场可编程门阵列、存储器等芯片的单粒子翻转率预估提供数据支撑,为我国卫星通信系统可靠性研究与设计提供参考．