THE effect of Srandom DOPANT fluctuation on threshold voltage and drain current variation in junctionless nanotransistors

We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation (10000 randomizations). With this simulation, we could study the effects of varying the dimensions (length and width), and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region (off) and overthreshold (on). It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion (compared with that of the subthreshold). These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

Using d-limonene as the non-aromatic and non-chlorinated solvent for the fabrications of high performance polymer light-emitting diodes and field-effect transistors

Aiming to environment protection, green solvents are crucial for commercialization of solution-processed optoelectronic devices. In this work, d-limonene, a natural product, was introduced as the non-aromatic and non-chlorinated solvent for processing of polymer light-emitting diodes (PLEDs) and organic field effect transistors (OFETs). It was found that d-limonene could be a good solvent for a blue-emitting polyfluorene-based random copolymer for PLEDs and an alternating copolymer FBT-Th₄(1,4) with high hole mobility (μ_h) for OFETs. In comparisons to routine solvent-casted films of the two conjugated polymers, the resulting d-limonene-deposited films could show comparable film qualities, based on UV–vis absorption spectra and observations by atomic force microscopy (AFM). With d-limonene as the processing solvent, efficient blue PLEDs with CIE coordinates of (0.16, 0.16), maximum external quantum efficiency of 3.57%, and luminous efficiency of 3.66 cd/A, and OFETs with outstanding μ_h of 1.06 cm² (V s)⁻¹ were demonstrated. Our results suggest that d-limonene would be a promising non-aromatic and non-chlorinated solvent for solution processing of conjugated polymers and molecules for optoelectronic device applications.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Measurement and Identification of the Parameters of SPICE-Models of a Bipolar Transistor

A method of measuring and identifying the static parameters of a bipolar transistor is considered. The characteristic of the transistor, from which the parameters of the model are determined, is chosen depending on what group the calculated parameters belong to. The characteristics are measured in such a way that the equations of the model describing them can be reduced to the simplest form.     

大功率晶体管的保护电路

大功率晶体管调速系统中作为开关元件使用时，共优点是开关频率比可控硅的高，但是不注意保护就容易损坏。着重研究过电流故障，并对保护作用的影响进行了分析，进而提出了防止过电流的方法和工作原理。     

浅谈低频小功率三极管的输入电阻的计算

就低频小功率三极管的输入电阻的计算进行了探讨。     

STI process steps for sub-quarter micron CMOS

This paper presents Shallow Trench Isolation (STI) process steps for sub-1/4 μ CMOS technologies. Dummy active areas, vertical trench sidewalls, excellent gap filling, counter mask etch step and CMP end point detection, have been used for a 0.18 μm CMOS technology. Electrical results obtained with a 5.5 nm gate oxide thickness show good isolation down to 0.3 μm spacing. Good transistor performances have been demonstrated.     

CMOS电路中抗Latch-up的保护环结构研究

闩锁是CMOS集成电路中的一种寄生效应,这种PNPN结构一旦被触发,从电源到地会产生大电流,导致整个芯片的失效。针对芯片在实际测试中发现的闩锁问题,介绍了闩锁的测试方法,并且利用软件Tsuprem4和Medici模拟整个失效过程,在对2类保护环(多子环/少子环)作用的分析,以及各种保护结构的模拟基础之上,通过对比触发电压和电流,得到一种最优的抗Latch up版图设计方法,通过进一步的流片、测试,解决了芯片中的闩锁失效问题,验证了这种结构的有效性。     

L波段窄脉宽500W固态功放组件的设计

介绍了作者研制的应用于固态雷达发射机上的L波段500W固态功放组件的工作原理、用途及其主要技术指标。描述了功放组件的设计过程和测试结果。该功放组件在窄脉宽条件下实现了快速上升沿,性能优良,工作稳定可靠。