高速PCB设计中GHz串行信号的完整性分析与仿真

文章针对信号频率超过GHz的高速串行信号带来的新的信号完整性问题,如:趋肤效应、介质损耗、码间串扰等进行了详细的分析;研究了这些信号完整性问题对于SI仿真的影响;给出解决GHz信号完整性问题的方案,并验证了方案的有效性。     

SCAN90CP02型LVDS交叉点开关的功能及应用

SCAN90CP02是美国国家半导体公司最新推出的LVDS超高速交叉点开关，具有的预增强功能使其可应用于高损耗的背板及电缆连接中以增强驱动能力。文中详细介绍该电路的功能、结构和配置方式，同时给出它的应用方法。     

甚短距离光互连模块技术的发展动态

甚短距离光互连技术作为一种突破铜线互连传输瓶颈有效方法,受到了广泛关注。半导体光学器件技术、高速化集成电路技术和光电模块封装技术作为实现光互连的关键技术发展较为迅速。首先阐述了垂直腔面发射激光器的电路模型,然后针对光信号发送模块介绍了预加重补偿技术以及开环方式稳定光功率输出技术,并对如何提高光信号接收模块带宽性能的电路技术进行了分析。其次结合光互连模块技术标准的发展,以NEC公司的实用化甚短距离并行光互连模块为例,对其光电封装技术进行了说明,最后就甚短距离光互连技术所面临的课题及发展前景进行了总结。     

信号完整性设计中的抖动与振铃消除技术

针对高速信号传输中码间干扰引起的抖动问题,提出了一种新型电流模式预加重电路,与传统结构相比,该新型电路不仅降低了电路复杂度,而且通过双边沿预加重提高了工作速度．针对低压差分信号传输的振铃问题,在考虑芯片压焊线模型以及负载的情况下,提出了一种基于阻抗匹配方法的振铃消除技术,有效缓解了输出振铃现象．通过对仿真和测试眼图进行讨论,验证了新方法的实用性．     

片上互连中Pre-emphasis电路的研究

随着SOC的发展,单个芯片上集成的内核越来越多,片上系统的复杂化对片上互连线的传输带宽以及可靠性提出了更高的要求.基于传输均衡原理的pre-emphasis技术通过在数据的发送端加强信号高频分量,衰减低频分量,能够有效地提高互连带宽,消除码间干扰.Pre-emphasis电路结构中的延时对电路性能有着很大的影响.通过对传输函数进行拉普拉斯变换,从理论上分析出存在使电路性能最佳的最优延时,该延时与信道的RC参数有关.基于SPICE的电路仿真表明,经过优化的pre-emphasis电路能够更有效地提高传输带宽,实现片上互连的高速传输.     

基于DCO-OFDM水下可见光通信系统的预均衡技术

针对硬件预均衡技术和基于有限脉冲响应(FIR)滤波器的软件预均衡技术存在的问题,提出了数字预加重的软件预均衡技术,该技术根据发光二极管(LED)的频率响应参数针对性地补偿LED带宽,并设计了一套直流偏置光-正交频分复用(DCO-OFDM)水下可见光通信系统作为实验测试平台.实验结果表明:采用数字预加重技术后,LED调制...     

基于级联变系数训练序列和预增强技术的直接检测光OFDM系统实验研究

分析了直接检测光OFDM(DDO-OFDM)传输系统中由数模转换器和光纤链路中的光纤色散所致的OFDM信号高频衰减现象,以及经光纤传输后在光电检测时存在的子载波间互拍干扰现象。提出使用级联变系数训练序列和预增强结构的光OFDM(O-OFDM)信号来降低传输系统所受到的影响。理论分析和实验验证表明,级联变系数训练序列和预增强结构的基带OFDM信号在DDO-OFDM传输系统中,接收灵敏度比常规的交叉型训练序列结构的OFDM信号要高。说明基于级联变系数训练序列和预增强结构的O-OFDM信号的传输性能在抵抗子载波间互拍干扰(SSMI)和频率选择性衰减(FF)方面要优于常规的交叉型训练序列结构的O-OFDM信号。     

Multi-Rate SerDes Transceiver for IEEE 1394b Applications

This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2 including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.     

A 5 Gb/s transceiver in 0.13μm CMOS for PCIE2.0

This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC’s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm~2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.     

一种应用于串行链路的5Gb/s低功耗电流模预加重发送器

A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode(VM) and current mode(CM) output driver architectures,a low power CM output driver with reverse scaling and bias current filtering technique is proposed.A 2-tap pre-emphasis filter is used to reduce the intersymbol interference caused by the low-pass channel,and a high speed,low power combined serializer is implemented to convert 10 bit parallel data into a serial data stream.The whole transmitter is fabricated in 65 nm 1.2 V/2.5 V CMOS technology.It provides an eye height greater than 800 mV for data rates of both 2.5 Gb/s and 5 Gb/s.The output root mean square jitter of the transmitter at 5 Gb/s is only 9.94 ps without pre-emphasis.The transmitter consumes 41.2 mA at 5 Gb/s and occupies only 240×140μm~2.