基于0.6 μm工艺的流水线模数转换器设计

为了实现10位高性能和低功耗的流水线模拟数字转换器ADC，提出了基于0.6微米互补型金属氧化物半导体(CMOS)混合信号工艺的电路设计方法.在信号输入端设置了采样保持放大器(SHA)，级电路中采用了低功耗运算跨导放大器(OTA)和动态比较器，并且使用了采样电容优化技术和数字校正技术.测试结果表明，在20 MHz采样率和5 MHz输入信号频率条件下，由该方法设计的ADC可以达到58 dB的信号噪声失调比(SNDR)，相当于9.38个有效位数(ENOB)，并且在5 V供电电压下的功耗仅为49 mW，达到了高SNDR性能、高线性度和低功耗的设计要求.     

A Self-Calibrated Pipeline ADC with 200 MHz IF-Sampling Frontend

A 13-bit, 50-MS/s pipeline ADC with IF-sampling capability is presented. A high sampling linearity is obtained through the use of bootstrapped switches. A digital self-calibration algorithm with modified capacitor measurement scheme is employed to improve the accuracy of the first two pipeline stages. The prototype, implemented with a 0.35-m BiCMOS (SiGe) technology, shows a 76.5-dB SFDR at a 194.2-MHz signal frequency and dissipates 715 mW power from a 2.9-V supply.     

一种高速高精度采样/保持电路

介绍了一种用于12bit,100MS/s流水线模数转换器前端的采样/保持电路的设计.该电路在3V电源电压100MHz采样频率时,输入直到奈奎斯特频率仍能够达到108dB的无杂散动态范围(SFDR)和77dB的信躁比(SNR).论文建立了考虑开关之后的采样保持电路的分析模型,并详细研究了电路中开关组合对电路性能的影响,同时发现了传统的栅源自举开关(bootstrapped switch)中存在的漏电现象并对其进行了改进,极大地减小了漏电并提高了电路的线性性能.     

一种应用于流水线ADC采样保持电路的设计

介绍了一种应用于12位、10MS/s流水线模数转换器前端的高性能采样保持（SH）电路的设计。该电路采用全差分电容翻转型结构及下极板采样技术,有效地减少噪声、功耗及电荷注入误差。采用一种改进的栅源电压恒定的自举开关,极大地减小电路的非线性失真。运算放大器为增益增强型折叠式共源共栅结构,能得到较高的带宽和直流增益。该采样保...     

High-gain,high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower

A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (g_mr₀)⁴ , obtained using a two-stage structure with cascoded stages, and is a two-stage Miller-compensated amplifier employing multipath to remove the positive zero. It has close to rail-to-rail output swing (limited by cascoding) and very low common-mode gain thanks to a replica technique (allowing the use of low-power common-mode feedback [CMFB] loops). Ninety-two decibels of gain and 176 dB of common-mode rejection ratio (CMRR) without CMFB are achieved using a 40-nm complementary metal-oxide semiconductor (CMOS) process. The OTA is used to design a low-power sample-and-hold amplifier (SHA) operating at 5 MSps, a typical application for CMOS OTAs, which has been chosen to verify the proposed circuit's performance and to show that the OTA is robust in Monte Carlo simulations under process variations and mismatches in an actual application.     

一种超宽带等效采样接收机的设计与实现

脉冲超宽带雷达回波信号由于带宽大而难以直接采样,通常采用等效时间采样方法来进行模数转换。传统的等效采样接收机大都是基于改变ADC采样时钟的时延来实现等效采样,采样时钟对触发信号会产生亚稳态时序,不可避免地会出现数据误对齐,必须添加辅助的在线或离线校正设计。针对这一问题,设计了一种基于FPGA内置延迟线的超宽带等效采样接收机,FPGA产生延时可调的发射触发信号去控制波形产生系统,基于高速采样保持器和ADC完成回波接收,实现了超宽带射频信号的等效采样,而无数据误对齐问题。接收机的等效采样速率为12.8GS/s,-3dB采样带宽为6.4GHz,满足脉冲超宽带雷达的应用需求。     

An S/H circuit with parasitics optimized for IF-sampling

An IF-sampling S/H is presented, which adopts a flip-around structure, bottom-plate sampling technique and improved input bootstrapped switches. To achieve high sampling linearity over a wide input frequency range, the floating well technique is utilized to optimize the input switches. Besides, techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance. The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit, 250 MS/s pipeline ADC. For 30 MHz input, the measured SFDR/SNDR of the ADC is 94.7 dB/68. 5dB, which can remain over 84.3 dB/65.4 dB for input frequency up to 400 MHz. The ADC presents excellent dynamic performance at high input frequency, which is mainly attributed to the parasitics optimized S/H circuit.     

基于预充电和双采样技术的 S/H 电荷共享消除技术

针对开关电容采样/保持(S/H)电路中由负载电容记忆效应引起的电荷共享问题进行了建模.电荷共享效应会导致运放建立幅度增加,根据所推导的运放建立总公式,得出建立幅度增加会增大对运放功耗和带宽要求,或者降低建立速度.为改善该现象,基于预充电思想和双采样技术提出了一种优化方案,能在保持原 S/H 电路速度不变时,消除电荷共享效应对运放功耗和带宽的额外要求.仿真实现的12位100Msps 双采样/保持电路证明了其有效性.     

用于流水线ADC的高精度SHA-Less电路

本文提出了一种适用于高速、高精度流水线ADC的无采样保持运算放大器(SHA-less)结构。使用可变电阻带宽修调电路以及MDAC与flash ADC的对称性设计,减少了两种单元电路间的采样误差,通过增加MDAC采样电容复位时钟和独立的flash ADC采样电容技术,消除了采样电容残留电荷引起的踢回噪声。本设计作为14位125-MS/s流水线ADC的前端转换级,基于ASMC 0.35- BiCMOS工艺的仿真和测试结果表明,前端转换级芯片面积1.4?2.9 mm2,使用带宽修调后,125 MHz采样,30.8 MHz输入信号下,SNR从63.8 dB提高到70.6 dB,SFDR从72.5 dB提高到81.3 dB,转换器的动态性能在150 MHz的输入信号频率下无明显下降。