Fabrication of high breakdown voltage silicon Schottky barrier diodes using various edge termination structures

In this work, the design and fabrication of Au/n-Si Schottky barrier diodes (SBDs) with various edge termination schemes, including a reduced-surface-field-type lateral super-junction, a polycrystalline silicon (poly-Si) floating ring, and a p⁺-poly-Si guard ring, are presented. Experimental results show that the reverse leakage current of the proposed SBDs was reduced and the breakdown voltage increased with an increase of the poly-Si width of the guard ring.It was found that the device and fabrication technology developed in the present study is applicable to the realization of SBDs with a high breakdown voltage (≥ 160 V), a low reverse current density (≤ 5.6 μA/cm²), a low forward voltage drop (≤ 5.6 V @ 1 A/cm²), and an adjustable Schottky barrier height of 0.764 to 0.784 eV.     

SiC超结MOSFET的短路特性研究

SiC超结MOSFET设计基于N/P柱的电荷补偿效应,在保证耐压的同时具有较低的导通损耗和更快的开关速度,因此对SiC超结MOSFET可靠性的分析研究有助于深入理解器件工作机理,为更好地应用提供必要的理论支撑。基于TCAD Sentaurus模拟软件,对1 200 V电压等级的传统SiC MOSFET结构和SiC超结MOSFET结构进行建模。首先对比了2种器件的基本电学参数,然后重点分析了短路特性差异,在相同短路条件下对器件内部的物理机理进行了分析。结果表明SiC超结MOSFET可以有效地提高器件的击穿电压和导通电阻,同时表现出更好的短路可靠性。进一步分析了不同的偏置电压下SiC超结MOSFET的短路特性,结果表明,随着外部施加偏置电压增加,器件的短路耐受时间减小,同时短路饱和电流也会相应增大。     

一种900V超结VDMOSFET器件的设计与仿真

功率MOSFET在现代电子工业中已经得到了广泛的运用,然而在高压功率MOSFET器件中,如何平衡功率MOSFET的击穿电压与导通电阻的冲突一直是研究热点。结合超结理论和传统功率VDMOSFET的生产工艺设计了一款高压超结VDMOSFET器件,运用半导体器件仿真软件对器件结构进行优化,得到P柱区和N柱区掺杂浓度和厚度的最优值和工艺参数。仿真结果表明,设计的超结VDMOSFET器件击穿电压和导通电阻分别为946 V和0.83Ω,很好地平衡了功率MOSFET击穿电压与导通电阻的冲突。     

A deep trench super-junction LDMOS with double charge compensation layer

A deep trench super-junction LDMOS with double charge compensation layer (DC DT SJ LDMOS) is proposed in this paper. Due to the capacitance effect of the deep trench which is known as silicon–insulator–silicon (SIS) capacitance, the charge balance in the super-junction region of the conventional deep trench SJ LDMOS (Con. DT SJ LDMOS) device will be broken, resulting in breakdown voltage (BV) of the device drops. DC DT SJ LDMOS solves the SIS capacitance effect by adding a vertical variable doped charge compensation layer and a triangular charge compensation layer inside the Con. DT SJ LDMOS device. Therefore, the drift region reaches an ideal charge balance state again. The electric field is optimized by double charge compensation and gate field plate so that the breakdown voltage of the proposed device is improved sharply, meanwhile the enlarged on-current region reduces its specific on-resistance. The simulation results show that compared with the Con. DT SJ LDMOS, the BV of the DC DT SJ LDMOS has been increased from 549.5 to 705.5 V, and the R_on,sp decreased to 23.7 mΩ·cm².     

基于超结结构的肖特基势垒二极管

在功率半导体器件中,高的反向击穿电压和低的正向导通电阻之间的矛盾关系是影响其发展的主要因素之一,选用超结结构替代功率半导体器件中的传统电压支持层能够有效缓解这一矛盾关系。该文设计和实现了一种超结肖特基二极管,其中的电压支持层采用P柱和N柱交替构成的超结结构。在器件的制作方面,选用成熟的单步微电子工艺,通过4次N型外延和4次选择性P型掺杂来实现超结结构。为便于对比分析,设计传统肖特基二极管和超结肖特基二极管的电压支持层厚度一致,且超结结构中P柱和N柱的杂质浓度均和传统肖特基二极管的电压支持层浓度一致。测试得到传统肖特基二极管的反向击穿电压为110 V,而超结肖特基二极管的反向击穿电压为229 V。表明采用超结结构作为功率半导体器件的电压支持层能够有效提高反向击穿电压,同时降低器件的正向导通电阻,并且当P柱区和N柱区内的电荷量一致时器件的击穿电压最高。     

超结的击穿机理与特性分析

利用ISE软件模拟了阻断状态下超结(SJ)的耗尽层与电场分布,从电场分布的角度解释了SJ的击穿机理.并分析关键参数,如P柱与n柱的宽度、浓度等变化对超结击穿电压的影响.结果表明,SJ的击穿机理与传统的圆柱型结不同,SJ的击穿并不发生在结面的拐点处.并且,通过调整边缘区域P柱或n柱的宽度和浓度来提高SJ器件耐压及其稳定性.     

半超结抑制RC-TIGBT Snapback效应机理与仿真

首次对半超结RC-TIGBT与传统RC-TIGBT的正向导通机理进行了比较研究。通过Silvaco TCAD软件仿真,模拟研究了Ydrift值、P-集电区宽度与N+短路区宽度等关键参数对Snapback效应的影响。结果表明,回退电压点随着Ydrift的减小而减小,且与Ydrift呈线性关系。对于底部集电极尺寸而言,回退电压点与P-集电区宽度有关,与N+短路区宽度基本无关。基于仿真结果,给出半超结RC-TIGBT的等效电路,并详细分析了半超结技术能抑制Snapback效应的原因。最后,对半超结RC-TIGBT的结构参数进行设计,提出一种能减小Snapback效应的有效方法。     

一种具有独特导通机理的新型超结IGBT

首次指出了超结IGBT这一新型功率半导体器件独特的导通机理并对其作了详细分析.通过TMAMEDICI仿真验证,超结IGBT耐压能力和正向导通能力都明显优于普通IGBT.并且发现,不同N柱、P柱掺杂浓度下器件的导通模式会在单极输运和双极输运之间相互改变,而这一特性是超结IGBT所独有的.也正是这一特殊的导通机理使得超结I...     

A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance

A new SOl self-balance （SB） super-junction （S J） pLDMOS with a self-adaptive charge （SAC） layer and its physical model are presented. The SB is an effective way to realize charges balance （CB）. The substrate-assisted depletion （SAD） effect of the lateral SJ is eliminated by the self-adaptive inversion electrons provided by the SAC. At the same time, high concentration dynamic self-adaptive electrons effectively enhance the electric field （EI） of the dielectric buried layer and increase breakdown voltage （BV）. E1 = 600 V/μm and BV =- 237 V are obtained by 3D simulation on a 0.375-μm-thick dielectric layer and a 2.5-μm-thick top silicon layer. The optimized structure realizes the specific on resistance （Ron,sp） of 0.01319Ω·cm2, FOM （FOM = BV2/R p） of 4.26 MW/cm2 under a 11 μm length （Ld） drift region.     

高压超结VDMOS结构设计

为改善高压功率VDMOS击穿电压和导通电阻之间的平方率关系,采用超结理论及其分析方法,结合电荷平衡理论,计算了超结VDMOS的理想结构参数,并利用仿真软件SILVACO对超结VDMOS的各个工艺参数(外延厚度,P柱掺杂剂量,阈值电压)进行了优化设计,对器件的正向导通特性和反向击穿特性进行了仿真分析。最终设计了一个击穿电压为815V,比导通电阻为23mΩ.cm2的超结VDMOS。