Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability

A technique for implementing totally symmetric Boolean functions using hierarchical modules is presented. First, a simple cellular module is designed for synthesizing unate symmetric functions. The structure is universal, admits a recursive design, and uses only 2-input AND-OR gates. A universal test set of size (n²/8 + 3n/4) for detecting all single stuck-at faults can be easily determined for an n-input module, where n = 2^k, k ≥ 3. General symmetric functions are then realized following a unate decomposition method. The synthesis procedure guarantees full robust path-delay fault testability in the circuit. Experimental results on several symmetric functions reveal that the hardware cost of the proposed design is low, and the number of paths in the circuit is reduced significantly compared to those of earlier designs. Results on circuit area and delay for a few benchmark examples are also reported. Hafizur Rahaman received the Bachelor of Electrical Engineering degree from the Bengal Engineering College, Calcutta University, India in 1986, the Master degree in Electrical Engineering, and the Ph.D. degree in computer science and engineering from the Jadavpur University, Calcutta, India in 1988 and 2003 respectively. He is currently chairing the Department of Information Technology, Bengal Engineering and Science University, Shibpur, India. His research interest includes logic synthesis and testing of VLSI circuits, fault-tolerant computing, and quantum computing. He has published several papers in well-known international journals and in reputed conference proceedings. He served in the Organizing Committee of the International Conference on VLSI Design in 2000 and 2005, and as the Registration Chair of the 2005 Asian Test Symposium (ATS), in Kolkata. Debesh K. Das received the Bachelor and Master degrees in electronics and telecommunication engineering, and the Ph.D. degree in computer science and engineering all from the Jadavpur University, Calcutta, India in 1982, 1984, and 1997 respectively. He is currently full professor at the Department of Computer Science and Engineering, Jadavpur University. He visited the University of Potsdam, Germany, the Asian Institute of Technology, Bangkok, the Abdus Salam International Center for Theoretical Physics, Trieste, Italy, and the Nara Institute of Science and Technology, Japan. His research work primarily focuses on logic synthesis and testing of VLSI circuits and fault-tolerant computing. He has published numerous papers in archival journals and refereed international conference proceedings. He served in the Organizing Committee of the International Conference on VLSI Design in 2000 and 2005. He also served as the Organizing Chair of the 2005 Asian Test Symposium (ATS). Bhargab B. Bhattacharya received the B.Sc. degree in physics from the Presidency College, Calcutta, the B.Tech. and M.Tech. degrees in radiophysics and electronics, and the Ph.D. degree in computer science all from the University of Calcutta, India. Since 1982, he has been on the faculty of the Indian Statistical Institute, Calcutta, where currently he is full professor. He held visiting professorship at the University of Nebraska-Lincoln, USA, and at the University of Potsdam, Germany. In 2005, he visited the Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur as VSNL Chair Professor. His research and teaching interest includes logic synthesis, testing and physical design of VLSI circuits, nanotechnology, graph and geometric algorithms, and image processing architecture. He is author of more than 180 papers published in archival journals and refereed conference proceedings, and inventor of 8 United States patents. Currently, he is collaborating with Intel Corporation, USA, and IRISA, France, for development of image processing hardware, chip layout analysis and design, and reconfigurable parallel computing tools. Dr. Bhattacharya is a Fellow of the Indian National Academy of Engineering, a Fellow of the National Academy of Sciences, India, and a recipient of the VASVIK Award for Electronic Sciences and Technology. He is on the editorial board of the Journal of Circuits, Systems, and Computers (World Scientific, Singapore, and the Journal of Electronic Testing—Theory and Applications (Springer).     

Design for Testability Using State Distances

The average distance between states is proposed as a new testabilitymeasure for finite state machines (FSMs). Also proposed is theconcept of center state to reduce distances in FSMs. This testfunction embedding technique has been shown to improve thetestability of sequential circuits with minimal overhead. Anoverview of several design-for-testability (DFT) andsynthesis-for-testability (SFT) methods for sequential circuits willalso be given in this paper. Experimental results have shown thatthe DFT approach is more advantageous than the SFT approach toimplement our test function. The contribution of this paper is toanalyze the trade-offs between several aspects of DFT and SFTtechniques.