Ultimate bearing capacity of strip footing resting on clay soil mixed with tire-derived aggregates

This study investigated the use of recycled tire-derived aggregate (TDA) mixed with kaolin as a method of increasing the ultimate bearing capacity ( UBC) of a strip footing. Thirteen 1g physical modeling tests were prepared in a rigid box of 0.6 m × 0.9 m in plan and 0.6 m in height. During sample preparation, 0%, 20%, 40%, or 60% (by weight) of powdery, shredded, small-sized granular (G 1–4 mm) or large-sized granular (G 5–8 mm) TDA was mixed with the kaolin. A strip footing was then placed on the stabilized kaolin and was caused to fail under stress-controlled conditions to determine the UBC. A rigorous 3D finite element analysis was developed in Optum G-3 to determine the UBC values based on the experimental test results. The experimental results showed that, except for the 20% powdery TDA, the TDA showed an increase in the UBC of the strip footing. When kaolin mixed with 20% G (5–8 mm), the UBC showed a threefold increase over that for the unreinforced case. The test with 20% G (1–4 mm) recorded the highest subgrade modulus. It was observed that the UBC calculated using finite element modeling overestimated the experimental UBC by an average of 9%.     

基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

Delay compensated control of the Stefan problem and robustness to delay mismatch

This paper presents a control design for the one‐phase Stefan problem under actuator delay via a backstepping method. The Stefan problem represents a liquid‐solid phase change phenomenon which describes the time evolution of a material's temperature profile and the interface position. The actuator delay is modeled by a first‐order hyperbolic partial differential equation (PDE), resulting in a cascaded transport‐diffusion PDE system defined on a time‐varying spatial domain described by an ordinary differential equation (ODE). Two nonlinear backstepping transformations are utilized for the control design. The setpoint restriction is given to guarantee a physical constraint on the proposed controller for the melting process. This constraint ensures the exponential convergence of the moving interface to a setpoint and the exponential stability of the temperature equilibrium profile and the delayed controller in the norm. Furthermore, robustness analysis with respect to the delay mismatch between the plant and the controller is studied, which provides analogous results to the exact compensation by restricting the control gain.     

Three-phase four-wire shunt active power filter based on the SOGI filter and Lyapunov function for DC bus control

The three-phase four-wire shunt active power filter (SAPF) was developed to suppress the harmonic currents generated by nonlinear loads, and for the compensation of unbalanced nonlinear load currents, reactive power, and the harmonic neutral current. In this work, we consider instantaneous reactive power theory (PQ theory) for reference current identification based on the following two algorithms: the classic low-pass filter (LPF) and the second-order generalized integrator (SOGI) filter. Furthermore, since an important process in SAPF control is the regulation of the DC bus voltage at the capacitor, a new controller based on the Lyapunov function is also proposed. A complete simulation of the resultant active filtering system confirms its validity, which uses the SOGI filter to extract the reference currents from the distorted line currents, compared with the traditional PQ theory based on LPF. In addition, the simulation performed also demonstrates the superiority of the proposed approach, for DC bus voltage control based on the Lyapunov function, compared with the traditional proportional-integral (PI) controller. Both novel approaches contribute towards an improvement in the overall performance of the system, which consists of a small rise and settling time, a very low or nonexistent overshoot, and the minimization of the total harmonic distortion (THD).     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

Estimation of power density in IMPATT using different materials

ABSTRACT

The RF output power dissipated per unit area is calculated using Runge-Kutta method for the high-moderate-moderate-high (n⁺-n-p-p⁺) doping profile of double drift region (DDR)-based impact avalanche transit time (IMPATT) diode by taking different substrate at Ka band. Those substrates are silicon, gallium arsenide, germanium, wurtzite gallium nitride, indium phosphide and 4H-silicon carbide. A comparative study regarding power dissipation ability by the IMPATT using different material is being presented thereby modelling the DDR IMPATT diode in a one-dimensional structure. The IMPATT based on 4H-SiC element has highest power density in the order of 10¹⁰ Wm^?2 and the Si-based counterpart has lowest power density of order 10⁶ Wm^?2 throughout the Ka band. So, 4H-SiC-based IMPATT should be preferable over others for the power density preference based application. This result will be helpful to estimate the power density of the IMPATT for any doping profile and to select the proper element for the optimum design of the IMPATT as far as power density is concerned in the Ka band. Also, we have focused on variation of power density with different junction temperatures and modelled the heat sink with analysis of thermal resistances.     

大气状态下AFM阳极氧化加工Si的研究

Si纳米氧化线是构筑基于Si的纳米器件的基础。通过AFM针尖诱导阳极氧化加工的n型Si(100)的实验得到凸出的n型Si(100)氧化物高度和偏置电压成线性关系,与针尖扫描速度成负对数关系,并在前人的基础上深化了AFM针尖诱导氧化加工的机理和理论模型,得到了合适的加工条件为偏压8 V和扫描速度1μm/s。     

智能化中高压变频器实载试验平台的实现

中、高压变频器产量越来越多，但试验手段大多比较落后，一般采用带电机空转的方法。本文介绍了一个高压变频器试验平台，通过该平台可以对电压等级在3kV～10kV、功率在5000kW以下的变频器进行实载试验。     

数字电路中电源电压瞬间下降的成因及改进

通过分析数字集成芯片多输出中电源电压瞬间下降的原因,对常规驱动电路结构进行改进。改进后单输出电路的峰值电流降为原来的2/3,再通过优化版图的电源布线,能有效防止电源电压下降,使芯片正常稳定地工作。