碳纳米管场效应晶体管紧凑模型研究进展

随着摩尔定律逼近极限,碳纳米管场效应晶体管(CNTFET)被认为是5 nm以下CMOS晶体管的有力替代者。CNTFET具有准一维结构,栅极可有效控制导电沟道的导通/关断;同时,载流子在沟道内可实现近弹道输运,具有极高的迁移率。因此,CNTFET在低电压环境下,可提供较大的电流传输能力,为实现纳米级超大规模模拟/逻辑电路提供了解决方案。文章综述了CNTFET紧凑模型的发展现状,分析了现阶段面临的漏极电流精确模型、隧穿效应、寄生效应、多纳米管模型等存在的问题,重点探讨了针对这些问题的解决方案。最后对该紧凑模型未来的应用前景进行了讨论。     

碳纳米管场效应晶体管电子输运特性的研究

由于硅器件尺寸不断缩小至纳米尺度,人们因此对纳米尺度器件开展了理论与结构方面的广泛而深入的研究,其中最重要的纳米尺度器件是基于碳纳米管的电场效应器件并被称为碳纳米管场效应晶体管(CNTFET).本文分析了碳纳米管场效应晶体管沟道电子的传输特性,并给出了用器件端子参数描述的器件I-V特性方程表达式,计算了器件的I-V特性曲线并把结果与纳米器件专用分析软件nanoMOS-2.0给出的结果作了比较,发现本文模型的计算结果均大于nanoMOS-2.0给出的结果,表明本文模型尚需进一步的深入分析和优化.     

High Precision SAR ADC Using CNTFET for Internet of Things

A high precision 10-bit successive approximation register analog to digital converter (ADC) designed and implemented in 32nm CNTFET process technology at the supply of 0.6V, with 73.24 dB SNDR at a sampling rate of 640 MS/s with the average power consumption of 120.2 μW for the Internet of things node. The key components in CNTFET SAR ADCs are binary scaled charge redistribution digital to analog converter using MOS capacitors, CNTFET based dynamic latch comparator and simple SAR digital code error correction logic. These techniques are used to increase the sampling rate and precision while ensuring the linearity, power consumption and noise level are within the limit. The proposed architecture has high scalability to CNTFET technology and also has higher energy efficiency. We compared the results of CNTFET based SAR ADC with other known architectures and confirm that this proposed SAR ADC can provide higher precision, power efficiency to the Internet of things node.     

异质栅碳纳米管场效应管电学特性研究

采用一种量子力学模型,研究了类MOSFET型碳纳米管场效应管(CNTFET)的电流特性.该模型基于二维非平衡格林函数(NEGF)方程和泊松(Poisson)方程自洽全量子数值解.结合器件的工作原理,研究了器件结构尺寸效应,比较分析单栅、异质栅CNTFET的电学特性.研究结果表明,与单橱结构相比,异质栅器件结构具有更低的泄漏电流、更高的电流开关比,并且,在15 nm技术节点以上,异质栅CNTFET器件能够较好地满足ITRS'10的相关性能指标要求.     

异质栅纳米碳管场效应管线性掺杂效应的研究

The effects of linear doping profile near the source and drain contacts on the switching and high- frequency characteristics for conventional single-material-gate CNTFET （C-CNTFET） and hetero-material-gate CNTFET （HMG-CNTFET） have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green＇s functions （NEGF） solved self-consistently with Poisson＇s equations. The simulation results show that at a CNT channel length of 20 nm with chirality （7, 0）, the intrinsic cutoff frequency of C-CNTFETs reaches up to a few THz. In addition, a comparison study has been performed between C-and HMG-CNTFETs. For the C-CNTFET, results reveal that a longer linear doping length can improve the cutoff frequency and switching speed. However, it has the reverse effect on on/off current ratios. To improve the on/off current ratios performance of CNTFETs and overcome short-channel effects （SCEs） in high-performance device applications, a novel CNTFET structure with a combination of an HMG and linear doping profile has been proposed. It is demonstrated that the HMG structure design with an optimized linear doping length has improved high-frequency and switching performances as compared to C-CNTFETs. The simulation study may be useful for understanding and optimizing high-performance of CNTFETs and assessing the reliability of CNTFETs for prospective applications.     

Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic

Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32 nm CNTFET technology at various realistic conditions such as different power supplies, load capacitors, frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even in the presence of PVT variations. In addition, new noise injection circuits for ternary logic are also presented to perform noise immunity analysis.     

Novel and general carbon nanotube FET-based circuit designs to implement all of the 3 ternary functions without mathematical operations

In this paper, we propose new universal designs of ternary-valued logic (TVL) with high-speed, low-power and full swing output using carbon nanotube FETs (CNTFETs). All of the TVL functions (3⁹ functions) can be implemented in these designs. Ternary value logic is a promising alternative to binary logic due to the reduced integrated circuit (IC) interconnects and chip area. Therefore, a universal design of TVL is a good direction for the future of FPGA design using CNTFET. In this paper, new universal designs of ternary-valued logic based on CNTFETs are proposed and compared with the existing resistive-load CNTFET universal TVL designs. Extensive simulations have been performed in HSPICE to investigate the distribution of power consumption and the delay of the CNTFET-based universal cells due to variations in the supply voltage, the diameter of the CNT, and the room temperature. Simulation results show that the proposed universal TVL designs result in significantly lower power consumption and delay compared with previous resistive-load CNTFET universal TVL implementations.     

单壁碳纳米管场效应晶体管的制备工艺研究

综述了碳纳米管场效应晶体管(CNTFET)的主要结构和导电沟道的制备工艺,如AFM探针操控、CVD原位生长、交流介电泳和L-B大面积操控排布等方法。在对CNTFET的这些结构和制备工艺进行详细分析的基础上,着重指出目前CNTFET导电沟道制备中存在的诸如金属性单壁碳纳米管(SWCNT)的烧除、接触电阻大、滞后现象以及p型CNTFET转化等问题,并针对这些问题提出了具体可行的解决方案。     

Dielectrophoresis‐Assisted Integration of 1024 Carbon Nanotube Sensors into a CMOS Microsystem

Carbon‐nanotube (CNT)‐based sensors offer the potential to detect single‐molecule events and picomolar analyte concentrations. An important step toward applications of such nanosensors is their integration in large arrays. The availability of large arrays would enable multiplexed and parallel sensing, and the simultaneously obtained sensor signals would facilitate statistical analysis. A reliable method to fabricate an array of 1024 CNT‐based sensors on a fully processed complementary‐metal‐oxide‐semiconductor microsystem is presented. A high‐yield process for the deposition of CNTs from a suspension by means of liquid‐coupled floating‐electrode dielectrophoresis (DEP), which yielded 80% of the sensor devices featuring between one and five CNTs, is developed. The mechanism of floating‐electrode DEP on full arrays and individual devices to understand its self‐limiting behavior is studied. The resistance distributions across the array of CNT devices with respect to different DEP parameters are characterized. The CNT devices are then operated as liquid‐gated CNT field‐effect‐transistors (LG‐CNTFET) in liquid environment. Current dependency to the gate voltage of up to two orders of magnitude is recorded. Finally, the sensors are validated by studying the pH dependency of the LG‐CNTFET conductance and it is demonstrated that 73% of the CNT sensors of a given microsystem show a resistance decrease upon increasing the pH value.     

Total-ionizing-dose effects and reliability of carbon nanotube FET devices

Electrical stress and 10-keV X-ray irradiation and annealing responses are evaluated for carbon nanotube field effect transistors for nonvolatile memory applications. Less than 3% change in the drain current is observed during constant-voltage stress. Irradiation and annealing under positive gate bias induces more degradation in both drain current and memory window than under negative bias. Cycling of the on/off state leads to significant degradation in the memory window.