A High Gain,Noise Cancelling 3.1-10.6 GHz CMOS LNA for UWB Application

With the rapid development of ultra-wideband communications, the design requirements of CMOS radio frequency integrated circuits have become increasingly high. Ultra-wideband (UWB) low noise amplifiers are a key component of the receiver front end. The paper designs a high power gain (S₂₁) and low noise figure (NF) common gate (CG) CMOS UWB low noise amplifier (LNA) with an operating frequency range between 3.1 GHz and 10.6 GHz. The circuit is designed by TSMC 0.13 μm RF CMOS technology. In order to achieve high gain and flat gain as well as low noise figure, the circuit uses many technologies. To improve the input impedance matching at low frequencies, the circuit uses the proposed T-match input network. To decrease the total dissipation, the circuit employs current reused technique. The circuit uses he noise cancelling technique to decreases the NF. The simulation results show a flat S₂₁>20.81 dB, the reverse isolation (S₁₂) less than -48.929 dB, NF less than 2.617 dB, the minimum noise figure (NF_min)=1.721 dB, the input return loss (S11) and output return loss (S₂₂) are both less than -14.933 dB over the frequency range of 3.1 GHz to 10.6 GHz. The proposed UWB LNA consumes 1.548 mW without buffer from a 1.2 V power supply.     

级联型低噪声放大器设计和优化的研究

文章详细分析了共源共栅级联型低噪声放大器的优化设计方法。文章首先简要的介绍共源共栅MOSFET低噪声放大器优化设计步骤。在此基础上，通过分析整个级联型低噪声放大器的密勒效应对优化设计的影响，进一步提出了对共栅级MOSFET的沟道宽度优化的必要性。最后，文章以一个工作于2．4GHz，0．5gm工艺的低噪声放大器设计为例，证实了前面理论分析的正确性，并根据低噪声放大器的主要设计指标给出了共源共栅结构下共栅级MOSFET的沟道宽度的优化方法。     

Low-noise differential transimpedance amplifier structure based on capacitor cross-coupled gm-boosting scheme

This paper presents a capacitor cross-coupled g_m-boosting scheme for differential implementation of common-gate transimpedance amplifier (CG-TIA). A differential transimpedance amplifiers (DTIA) is designed by this scheme using two modified floating-biased CG stage with improved low corner frequency. Despite conventional methods for single-ended to differential conversion that increase the power and the noise for the same gain, the new DTIA gives a higher gain and hence reduces the input-referred noise power. Design of the DTIA circuit using 0.13 μm CMOS technology illustrates near 1.7 dB improvement in the circuit sensitivity and 5.2 dB enhancement in transimpedance gain compared to its single-ended counterpart. Operation at very low frequencies and stable dc coupling to photodiode are other features of the proposed DTIA.     

一种高增益宽带共栅CMOS电流模跨阻放大器

文章提出了一种高增益宽带共栅CMOS电流模跨阻放大器，从理论上对电路进行了分析。采用0．5μm CMOS工艺进行HSPICE仿真，结果表明，该电路结构能达到57dBΩ跨阻增益，1．5GHz带宽，6．4pA／sqrt(Hz)等效输入总电流噪声；在输入电流为200pA时，其输出电压的动态摆幅达到220mV，功耗仅为76mW。