Effects of hot-carrier stress on high performance polycrystalline silicon thin film transistor with a single perpendicular grain boundary

This paper is a report on the effect of a single perpendicular grain boundary on the hot-carrier and high current stability in high performance polycrystalline silicon (poly-Si) thin film transistors (TFTs). Under a hot carrier stress condition (Vg = Vth + 1 V, Vd = 12 V), the poly-Si TFT with a single grain boundary is superior to the poly-Si without any grain boundary because of the smaller free carriers available for electric conduction. The shift of transconductance in poly-Si TFT with a single grain boundary is less than 5% after hot carrier stress during a period of 1000 s. The shift of transconductance is about 25% in the case of the poly-Si TFTs without a grain boundary in the channel. On high current stress, the poly-Si TFT without the grain boundary is less degraded than the poly-Si TFT with the grain boundary because the concentrated electric field near the drain junction is lower.     

A Capacitor Voltage Clamped Dual Half-Bridge Series-Resonant Inverter for Home Cooking Applications

An induction heating appliance used for cooking includes more than one inductor, each being controlled by a separate inverter system. The main aim of this paper is to control each coil separately at a different frequency and power output by using the same inverter system. A working coil of two parts has been designed practically and a computer simulation has been carried out, using practical coil parameters. Each part of the coil has been operated at a different frequency and power output, which allows the use of vessels of two different diameters while obtaining a high coupling factor for both conditions. This also increases the efficiency of the system and improves power quality. The proposed topology can be applied to induction hotplates made up of several inductors in which the power and frequency must be separately regulated.     

用于LDD和SST的SiO2边墙干法腐蚀工艺研究

本文从干法腐蚀角度出发,首先从数学上分析了多晶硅角度,SiO_2边墙的宽度和高度,衬底损失与各工艺参数间的关系,指出边墙的宽度和高度分别取决于多晶硅的角度和过腐蚀量。在Tegal1512e设备上,采用Cl_2、SF_6、N_2混合气体,开发了多晶硅干法腐蚀工艺,讨论了LDD的正胶掩膜及SST的SiO_2掩膜对工艺的不同影响。SEM分析发现了SF_6气体腐蚀的各向同性。在Tegal903e设备上,采用CHF_3、SF_6、He混合气体,开发了SiO_2边墙干法腐蚀工艺,研究了腐蚀的各向异性,辐射损伤,选择比,均匀性及重复性的控制方法。取得的工艺结果为,腐蚀速率(?)_(sio_2)≈400nm/min,均匀性U≤±5％,选择比S_(f8)>10,工序能力指数C_p>1。     

Dependence of off-leakage current on channel film quality in poly-Si thin-film transistors and analysis using device simulation

The dependence of off-leakage current on channel film quality in poly-Si thin-film transistors has been analyzed using two-dimensional device simulation. It is found that the off-leakage current decreases as the intragrain trap density decreases for the low V_gs. This is because the Phonon-assisted tunneling with Poole-Frenkel effect is the dominant mechanism of the carrier generation and the generation rate of carrier pair decreases as the intragrain trap density decreases. On the other hand, the off-leakage current slightly increases as the intragrain trap density decreases for the high V_gs. This is because the band-to-band tunneling is the dominant mechanism and the influence of the intragrain trap density to the carrier conductance is larger than that to the generation rate.     

Multi-material gate poly-crystalline thin film transistors: Modeling and simulation for an improved gate transport efficiency

In this work, a two-dimensional potential distribution formulation is presented for multi-material gate poly-crystalline silicon thin film transistors. The developed formulation incorporates the effects due to traps and grain-boundaries. In short-channel devices, short-channel effects and drain-induced barrier lowering (DIBL) effect exists, and are accounted for in the analysis. The work aims at the reduction of DIBL effect and grain-boundary effects i.e. to reduce the potential barriers generated in the channel by employing gate-engineered structures. A study of work-functions and electrode lengths of multi-material gate electrode is done to suppress the potential barriers, hot electron effect and to improve the carrier transport efficiency. Green's function approach is adopted for the two-dimensional potential solution. The results obtained show a good agreement with simulated results, thus, demonstrating the validity of our model.     

Improving hydrogenation efficiency of polycrystalline silicon thin film transistors by a new approach

In this paper, a new hydrogenation process of poly-Si thin film for the fabrication of poly-Si thin film transistors (TFTs) is proposed. In the new approach, the hydrogenation of TFTs is performed before deposition of contact metal. N-channel and p-channel poly-Si TFTs with various channel lengths and widths were fabricated with the new and conventional processes for comparison. The results verified that the efficiency of hydrogenation has been improved remarkably by the new process. The field-effect mobility of carriers, the on state current, threshold voltage and the on/off states current ratio have been greatly improved, and the trap state density has been reduced significantly.     

Enhancement of optical absorption for below 5 μm thin-film poly-Si solar cell on glass substrate

Optical confinement effect of thin-film polycrystalline-Si (poly-Si) solar cell on glass substrate fabricated at low-temperature has been investigated as a function of cell thickness of less than 5 μm. We found that it is possible to fabricate the textured Si thin film in situ on a glass substrate and that the reflectance at long-wavelength light is reduced by surface texturing. Thin-film poly-Si solar cell and a-Si:H/(0.45 μm)/poly-Si (5 μm) tandem solar cell exhibit the efficiency of 8.6% and 12.8%, respectively. The numerical study in terms of the light trapping explains the excellent high short-circuit current density (_sc above 27 mA/cm² at the 4.7 μm thin-film poly-Si solar cell.     

高速BiCMOS工艺研究

研究开发了一种准２μｍ高速ＢｉＣＭＯＳ工艺，采用自对准双埋双阱及外延结构．外延层厚度为２．０～２．５μｍ，器件间采用多晶硅缓冲层局部氧化（简称ＰＢＬＯＣＯＳ）隔离，双极器件采用多晶硅发射极（简称ＰＳＥ）晶体管．利用此工艺已试制出ＢｉＣＭＯＳ２５级环振电路，在负载电容ＣＬ＝０．８ｐＦ条件下，平均门延迟时间ｔｐｄ＝０．８４ｎｓ，功耗为０．３５ｍＷ／门，驱动能力为０．６２ｎｓ／ｐＦ．明显优于ＣＭＯＳ门．     

Degradation evaluation of poly-Si TFTs by comparing normal and reverse characteristics and behavior analysis of hot-carrier degradation

We propose degradation evaluation of poly-Si TFTs by comparing normal and reverse characteristics. Since symmetrical normal and reverse characteristics indicate Joule-heating degradation whereas asymmetrical characteristics indicate hot-carrier degradation, they can be clearly and easily classified. Moreover, degradation occurrence is contrasted between standard and fine TFTs. Finally, behavior of the hot-carrier degradation is analyzed.     

Metal silicide/poly-Si Schottky diodes for uncooled microbolometers

Nickel silicide Schottky diodes formed on polycrystalline Si 〈P〉 films are proposed as temperature sensors of monolithic uncooled microbolometer infrared focal plane arrays. The structure and composition of nickel silicide/polycrystalline silicon films synthesized in a low-temperature process are examined by means of transmission electron microscopy. The Ni silicide is identified as a multi-phase compound composed of 20% to 40% of Ni₃Si, 30% to 60% of Ni₂Si, and 10% to 30% of NiSi with probable minor content of NiSi₂ at the silicide/poly-Si interface. Rectification ratios of the Schottky diodes vary from about 100 to about 20 for the temperature increasing from 22℃ to 70℃; they exceed 1,000 at 80 K. A barrier of around 0.95 eV is found to control the photovoltage spectra at room temperature. A set of barriers is observed in photo-electromotive force spectra at 80 K and attributed to the Ni silicide/poly-Si interface. Absolute values of temperature coefficients of voltage and current are found to vary from 0.3%℃ to 0.6%/℃ for forward bias and around 2.5%/℃ for reverse bias of the diodes.