PMSS: A programmable memory system and scheduler for complex memory patterns

HPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. However, applications are getting more complex, with multiple kernels and complex data arrangements, generating overhead while scheduling/managing system resources. Due to this reason all classes of multi threaded machines–minicomputer to supercomputer–require to have efficient hardware scheduler and memory manager that improves the effective bandwidth and latency of the DRAM main memory. This architecture could be a very competitive choice for supercomputing systems that meets the demand of parallelism for HPC benchmarks. In this article, we proposed a Programmable Memory System and Scheduler (PMSS), which provides high speed complex data access pattern to the multi threaded architecture. This proposed PMSS system is implemented and tested on a Xilinx ML505 evaluation FPGA board. The performance of the system is compared with a microprocessor based system that has been integrated with the Xilkernel operating system. Results show that the modified PMSS based multi-accelerator system consumes 50% less hardware resources, 32% less on-chip power and achieves approximately a 19x speedup compared to the MicroBlaze based system.     

支持远程动态重构的嵌入式系统设计

为使嵌入式系统具备远程在线更新和维护能力,基于软/硬件统一多任务编程模型,应用互联网可重构逻辑设计方法设计并实现支持远程动态重构的嵌入式系统。提出的统一多任务编程模型为软/硬件任务提供统一接口和管理方式,可降低设计可重构系统的复杂度,同时远程重构功能增加了系统远程在线更新和维护的能力。实验结果表明,该模型可用于远程可重构系统的设计,同时硬件任务也具有较快的加速比。     

基于SOPC高速图像实时处理技术研究与实现

本文针对现今高速数字图像信号的复杂算法实时处理要求以及系统实时升级问题,设计一种基于FPGA的SOPC高速图像实时处理系统平台,移植可定制高效操作系统Xilkernel,并采用多线程编程、软件仿真以及在线实时调试方法,成功地实现了高速系统实时处理功能.FPGA操作可并行执行及硬件反应时间精确到纳秒(ns)级,因而该系统...