一种计算机实时控制系统的分析及其DCS实现

简述了计算机实时控制及分布式控制系统(DCS)的一般特点．并以某型水下机器人的控制系统为例，详细介绍了一种小型实时DCS系统的具体实现。     

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.     

以CGA卡为基础的智能显示系统

本文介绍了以微处理器与ＩＢＭ－ＰＣ上的彩色／图形适配器相结合构成的一种智能显示系统。本系统主要解决数控系统中主ＣＰＵ与６８４５ＣＲＴＣ争夺显示缓存的矛盾。保证了６８４５ＣＲＴＣ对显示缓存操作的时间要求；并且保证了数控系统中主ＣＰＵ对显示缓存操作的随意性。     

Trade-offs in scan path and BIST implementations for RAMs

In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.     

一种高性能图形板的设计与实现

介绍了一种采用高性能嵌入式图形处理器、大容量双端口视频存储器、高性能查色表以及超大规模可编程逻辑器件设计的图形显示控制板的基本组成和工作原理。     

内嵌RAM的液晶显示控制驱动器

讨论一种液晶控制驱动器的设计及使用方法。根据设计要求，阐述了每个分模块的设计思想与设计方法，并进行了数模混合仿真。     

YH-F2的处理机间通讯

银河仿真Ⅱ型机ＹＨ－Ｆ２是高性能的全数字仿真计算机，处理机间通讯是ＹＨ－Ｆ２采用的关键技术之一。本文分三个部分介绍了ＹＨ－Ｆ２的处理机间通讯：①处理机通讯指令，③处理机间数据传输，③Ｉ／Ｏ处理机ＩＯＰ与通讯控制处理机ＣＣＰ之间的通讯。     

基于FPGA的高速数据存储系统优化设计

针对遥测系统数据记录装置中数据传输速率与存储速率不匹配的问题,提出Flash的并行存储方案,采用交替双平面的编程方式可以使得存储器的存储速率达到单片Flash最高存储速率的2倍,即60 MB/s;对控制单元FPGA内部双端口RAM的逻辑设计进行改进,解决了数据存储异常的现象。在数据回收方面,提出了多备份的设计思想和备用读数接口的设计方案,已在工程应用中得到成功实践,验证了该数据记录装置的可靠性。     

Event-driven,pattern-based methodology for cost-effective development of standardized personal health devices

Experiences applying standards in personal health devices (PHDs) show an inherent trade-off between interoperability and costs (in terms of processing load and development time). Therefore, reducing hardware and software costs as well as time-to-market is crucial for standards adoption. The ISO/IEEE11073 PHD family of standards (also referred to as X73PHD) provides interoperable communication between PHDs and aggregators. Nevertheless, the responsibility of achieving inexpensive implementations of X73PHD in limited resource microcontrollers falls directly on the developer. Hence, the authors previously presented a methodology based on patterns to implement X73-compliant PHDs into devices with low-voltage low-power constraints. That version was based on multitasking, which required additional features and resources. This paper therefore presents an event-driven evolution of the patterns-based methodology for cost-effective development of standardized PHDs. The results of comparing between the two versions showed that the mean values of decrease in memory consumption and cycles of latency are 11.59% and 45.95%, respectively. In addition, several enhancements in terms of cost-effectiveness and development time can be derived from the new version of the methodology. Therefore, the new approach could help in producing cost-effective X73-compliant PHDs, which in turn could foster the adoption of standards.