Cognitive abilities,digital games and arithmetic performance enhancement: A study comparing the effects of a math game and paper exercises

Besides entertainment, games have shown to have the potential to impact a broader variety of cognitive abilities. Research has consistently shown that several aspects in cognition such as visual short-memory, multitasking and spatial skills can be enhanced by game play. In a previous study, it was found that playing Monkey Tales, a game aimed at training arithmetic skills, helped second grade pupils to increase their accuracy in mental calculation as compared to paper exercises. In this follow up study we explore whether traditional methods and game training differ in terms of the cognitive processes that both are able to impact. We incorporated standardized measures of working memory and visuo-motor skills. Additionally, the mathematics game was modified and its contents extracted to allow precise comparison between the gaming and paper exercises condition. Thus each single math exercise, type of question (e.g., multiple choice), quantity and order was perfectly matched in the game training and the traditional training conditions. Gains in arithmetical performance, and self-reported measures of enjoyment were also investigated. We found some evidence suggesting that arithmetic performance enhancement induced by game play and paper exercises differ not only in terms of enjoyment but also of working memory capacity improvements.     

Resistive switching characteristics of ZnO–graphene quantum dots and their use as an active component of an organic memory cell with one diode-one resistor architecture

We investigated the resistive switching characteristics of a polystyrene:ZnO–graphene quantum dots system and its potential application in a one diode-one resistor architecture of an organic memory cell. The log–log I–V plot and the temperature-variable I–V measurements revealed that the switching mechanism in a low-current state is closely related to thermally activated transport. The turn-on process was induced by a space-charge-limited current mechanism resulted from the ZnO–graphene quantum dots acting as charge trap sites, and charge transfer through filamentary path. The memory device with a diode presented a ∼10³ I_ON/I_OFF ratio, stable endurance cycles (10² cycles) and retention times (10⁴ s), and uniform cell-to-cell switching. The one diode-one resistor architecture can effectively reduce cross-talk issue and realize a cross bar array as large as ∼3 kbit in the readout margin estimation. Furthermore, a specific word was encoded using the standard ASCII character code.     

Cued recall from image and sentence memory: A shift from episodic to identical elements representation.

The applicability of the identical elements (IE) model of arithmetic fact retrieval (T. C. Rickard, A. F. Healy, & L. E. Bourne, 1994) to cued recall from episodic (image and sentence) memory was explored in 3 transfer experiments. In agreement with results from arithmetic, speedup following even minimal practice recalling a missing word from an episodically bound word triplet did not transfer positively to other cued recall items involving the same triplet. The shape of the learning curve further supported a shift from episode-based to IE-based recall, extending some models of skill learning to cued recall practice. In contrast with previous findings, these results indicate that a form of representation that is independent of the original episodic memory underlies cued-recall performance following minimal practice. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

嵌人式与独立存储器设计上的差异分析和研究

进入21世纪,随着集成电路的发展,SoC(System on Chip)片上系统应运而生。而作为SoC重要组成部分的嵌入式存储器,在SoC中所占的比重正逐步增加,并起着越来越重要的作用,那么嵌入式存储器与独立的存储器芯片在设计上存在着哪些差异?对此本文将以NOR型闪存为例在制造工艺的选取、衍生产品的设计、功耗与噪声、后端功能仿真、测试与修复等方面进行分析和研究。     

Implementing Qubits with Superconducting Integrated Circuits

Superconducting qubits are solid state electrical circuits fabricated using techniques borrowed from conventional integrated circuits. They are based on the Josephson tunnel junction, the only non-dissipative, strongly non-linear circuit element available at low temperature. In contrast to microscopic entities such as spins or atoms, they tend to be well coupled to other circuits, which make them appealling from the point of view of readout and gate implementation. Very recently, new designs of superconducting qubits based on multi-junction circuits have solved the problem of isolation from unwanted extrinsic electromagnetic perturbations. We discuss in this review how qubit decoherence is affected by the intrinsic noise of the junction and what can be done to improve it. PACS: 03.67.-a, 03.65.Yz, 85.25.-j, 85.35.Gv     

Context-Processing Deficits in Schizotypal Personality Disorder.

Research suggests that schizotypal personality disorder (SPD) is a part of the spectrum of schizophrenia-related illnesses. This article hypothesizes that a deficit in the representation and maintenance of context is a core cognitive disturbance in schizophrenia and that SPD individuals should demonstrate context-processing deficits. To test this hypothesis, the authors administered 3 versions of their AX-CPT task, designed to assess context processing, to 35 healthy controls and 26 individuals with DSM-IV SPD. They also administered working memory and selective attention tasks. SPD individuals displayed context representation deficits similar to those found in schizophrenia but did not show the same additional deficits in context maintenance. Context processing was strongly associated with working memory and selective attention performance in the SPD individuals. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Allocentric Versus Egocentric Spatial Memory After Unilateral Temporal Lobectomy in Humans.

Thirty patients who had undergone either a right or left unilateral temporal lobectomy (14 RTL; 16 LTL) and 16 control participants were tested on a computerized human analogue of the Morris Water Maze. The procedure was designed to compare allocentric and egocentric spatial memory. In the allocentric condition, participants searched for a target location on the screen, guided by object cues. Between trials, participants had to walk around the screen, which disrupted egocentric memory representation. In the egocentric condition, participants remained in the same position, but the object cues were shifted between searches to prevent them from using allocentric memory. Only the RTL group was impaired on the allocentric condition, and neither the LTL nor RTL group was impaired on additional tests of spatial working memory or spatial manipulation. The results support the notion that the right anterior temporal lobe stores long-term allocentric spatial memories. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Mixed Mode VLSI Implementation of a Neural Associative Memory

A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. To keep the memory density as high as possible two design strategies are considered. First, the number of transistors per storage element is kept to a minimum. In this paper a circuit technique that uses a single 6-transistor cell for weight storage and analog signal processing is proposed. Second, the device precision has been chosen to a moderate level to save area as much as possible. Since device mismatch limits the performance of analog circuits, the impact of device precision on the circuit performance is explicitly discussed. It is shown that the device precision limits the number of rows activated in parallel. Since the input vector as well as the output vector are considered to be sparsely coded it is concluded, that even for large matrices the proposed circuit technique is appropriate and ultra large scale integration with a large number of connection weights is feasible.     

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.