Non-Volatile Electrolyte-Gated Transistors Based on Graphdiyne/MoS2 with Robust Stability for Low-Power Neuromorphic Computing and Logic-In-Memory

Artificial synapses are the key building blocks for low-power neuromorphic computing that can go beyond the constraints of von Neumann architecture. In comparison with two-terminal memristors and three-terminal transistors with filament-formation and charge-trapping mechanisms, emerging electrolyte-gated transistors (EGTs) have been demonstrated as a promising candidate for neuromorphic applications due to their prominent analog switching performance. Here, a novel graphdiyne (GDY)/MoS₂-based EGT is proposed, where an ion-storage layer (GDY) is adopted to EGTs for the first time. Benefitting from this Li-ion-storage layer, the GDY/MoS₂-based EGT features a robust stability (variation < 1% for over 2000 cycles), an ultralow energy consumption (50 aJ µm⁻²), and long retention characteristics (>10⁴ s). In addition, a quasi-linear conductance update with low noise (1.3%), an ultrahigh G_max/G_min ratio (10³), and an ultralow readout conductance (<10 nS) have been demonstrated by this device, enabling the implementation of the neuromorphic computing with near-ideal accuracies. Moreover, the non-volatile characteristics of the GDY/MoS₂-based EGT enable it to demonstrate logic-in-memory functions, which can execute logic processing and store logic results in a single device. These results highlight the potential of the GDY/MoS₂-based EGT for next-generation low-power electronics beyond von Neumann architecture.     

基于RRAM双交叉阵列结构的三值存内逻辑电路设计

在RRAM交叉阵列结构中实现逻辑运算可以较好地解决传统冯诺依曼架构中的存储墙问题.三值逻辑相比于传统的二值逻辑,具有更少的逻辑操作数目和更快的运算速度.文中提出了一种基于RRAM双交叉阵列结构的三值存内逻辑电路设计,其中三值逻辑电路的输入与输出均通过多值RRAM的阻值表示.该结构支持两种三值逻辑门和一种二值逻辑门以提升...     

Zero-static-power nonvolatile logic-in-memory circuits for flexible electronics

Flexible logic circuits and memory with ultra-low static power consumption are in great demand for battery-powered flexible electronic systems.Here,we show that a flexible nonvolatile logic-in-memory circuit enabling normally-off computing can be implemented using a poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (pV3D3)-based memristor array.Although memristive logic-in-memory circuits have been previously reported,the requirements of additional components and the large variation of memristors have limited demonstrations to simple gates within a few operation cycles on rigid substrates only.Using memristor-aided logic (MAGIC) architecture requiring only memristors and pV3D3-memristor with good uniformity on a flexible substrate,for the first time,we experimentally demonstrated our implementation of MAGIC-NOT and-NOR gates during multiple cycles and even under bent conditions.Other functions,such as OR,AND,NAND,and a half adder,are also realized by combinations of NOT and NOR gates within a crossbar array.This research advances the development of novel computing architecture with zero static power consumption for batterypowered flexible electronic systems.     

Switchable Polar Nanotexture in Nanolaminates HfO2-ZrO2 for Ultrafast Logic-in-Memory Operations

Nontrivial topological polar textures in ferroelectric materials, including vortices, skyrmions, and others, have the potential to develop ultrafast, high-density, reliable multilevel memory storage and conceptually innovative processing units, even beyond the limit of binary storage of 180° aligned polar materials. However, the realization of switchable polar textures at room temperature in ferroelectric materials integrated directly into silicon using a straightforward large area fabrication technique and effectively utilizing it to design multilevel programable memory and processing units has not yet been demonstrated. Here, utilizing vector piezoresponse force and conductive atomic force microscopy, microscopic evidence of the electric field switchable polar nanotexture is provided at room temperature in HfO₂-ZrO₂ nanolaminates grown directly onto silicon using an atomic layer deposition technique. Additionally, a two-terminal Au/nanolaminates/Si ferroelectric tunnel junction is designed, which shows ultrafast (≈83 ns) nonvolatile multilevel current switching with high on/off ratio (>10⁶), long-term durability (>4000 s), and giant tunnel electroresistance (10⁸%). Furthermore, 14 Boolean logic operations are tested utilizing a single device as a proof-of-concept for reconfigurable logic-in-memory processing. The results offer a potential approach to “processing with polar textures” and addressing the challenges of developing high-performance multilevel in-memory processing technology by virtue of its fundamentally distinct mechanism of operation.