A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.     

几种新型的光电器件

描述用ＳＯＩ技术制造的光耦合ＭＯＳ继电器和多量子阱长波和红外探测器，以及集成异质结晶体管和激光二管于一体的高增益，高灵敏的光电子开关器件，文中着重介绍这些器件的结构，制造工和器件特性，并对其进行了讨论。     

SOI全介质隔离与高频互补双极兼容工艺

ＳＯＩ材料的全介质隔离技术与高频互补双极工艺的结合是研制抗辐照能力强、频带宽、速度高的集成运算放大器的理想途径，从实验的角度提出了一种ＳＯＩ材料全介质隔离与高频互补双极工艺兼容的工艺途径。     

激光结晶a-Si:H SOI离子注入和快速退火

本文对激光结晶a-Si∶H SOI结构砷注入和快速退火行为作了研究.a-Si∶H激光结晶有Lp-LCR,OD,FCR-2,FCR-1四个结晶区.用剖面电镜观察了结晶区的结构.扩展电阻测量表明Lp-LCR区中有两种扩散机制,即杂质在晶粒体内扩散和沿缺陷扩散.OD区中有三种扩散形式,除有上述两种以外,还有沿缺陷的扩散.首次比较了沿晶界和缺陷的扩散速度.     

Plasma immersion ion implantation for SOI synthesis: SIMOX and ion-cut

We have demonstrated feasibility to form silicon-on-insulator (SOI) substrates using plasma immersion ion implantation (PIII) for both separation by implantation of oxygen and ion-cut. This high throughput technique can substantially lower the high cost of SOI substrates due to the simpler implanter design as well as ease of maintenance. For separation by plasma implantation of oxygen wafers, secondary ion mass spectrometry analysis and cross-sectional transmission electron micrographs show continuous buried oxide formation under a single-crystal silicon overlayer with sharp Si/SiO₂ interfaces after oxygen plasma implantation and high-temperature (1300°C) annealing. Ion-cut SOI wafer fabrication technique is implemented for the first time using PIII. The hydrogen plasma can be optimized so that only one ion species is dominant in concentration and there are minimal effects by other residual ions on the ion-cut process. The physical mechanism of hydrogen induced silicon surface layer cleavage has been investigated. An ideal gas law model of the microcavity internal pressure combined with a two-dimensional finite element fracture mechanics model is used to approximate the fracture driving force which is sufficient to overcome the silicon fracture resistance.     

离子注入半导体的快速热退火与SOI技术

自1977年以来,为了摸索离子注入半导体的新退火方法,各国学者进行了大量的研究工作。这种努力是从激光退火的研究开始的。激光与半导体材料相互作用的研究,已派生出若干很有生命力的应用项目,其中,快速热退火、SOI(Semiconductor on Insulator)技术等已显示了重要的应用前景,并正在走向实用化。     

CMOS兼容近红外Si0.7Ge0.3/Si p-i-n(SOI)光电探测器

报道了一种采用UHV/CVD锗硅工艺和CMOS工艺流程在SOI衬底上制作的横向叉指状Si0.7Ge0.3/Si p-i-n光电探测器.测试结果表明:其工作波长范围为0.7～1.1μm,在峰值响应波长为0.93μm,响应度为0.38A/W.在3.0V的偏压下,其暗电流小于1nA,寄生电容小于1.0pF,上升时间为2.5ns.其良好的光电特性以及与CMOS工艺的兼容性,为研制能有效工作于近红外光的高速、低工作电压硅基光电集成器件提供了一种新的尝试,在高速光信号探测等应用中有一定的价值.     

一种低压低功耗SRAM/SOI单元设计

提出一种改进4管自体偏压结构SRAM/SOI单元.基于TSUPREM4和MEDICI软件的模拟和结构性能的分析,设计单元结构并选取结构参数.该结构采用nMOS栅下的含p+埋沟的衬底体电阻代替传统6管CMOSSRAM单元中的pMOS元件,具有面积小、工艺简单的优点.该结构可以在0.5V的电源电压下正常工作,与6管单元相比,该单元瞬态响应正常,功耗只有6管单元的1/10,满足低压低功耗的要求.     

基于SOI的硅微谐振式压力传感器芯片制作

采用SOI硅片,基于MEMS技术,设计并加工了一种新型三明治结构的硅微谐振式压力传感器,根据传感器敏感单元的结构设计,制定了相应的制备工艺步骤,并且针对湿法深刻蚀过程中谐振子的刻蚀保护等问题,提出了一种基于氮化硅、氧化硅和氮化硅三层薄膜的保护工艺,实验表明,在采用三层薄膜保护工艺下进行湿法刻蚀10 h后,谐振子被完全释放,三层薄膜保护工艺对要求采用湿法刻蚀镂空释放可动结构具有较高的实用价值。最后对加工完成的谐振式压力传感器进行了初步的性能测试,结果表明,在标准大气压力下谐振子的固有频率为9.932 kHz,品质因数为34。     

Multi-channel micro neural probe fabricated with SOI

Silicon-on-insulator(SOI) substrate is widely used in micro-electro-mechanical systems(MEMS).With the buried oxide layer of SOI acting as an etching stop,silicon based micro neural probe can be fabri-cated with improved uniformity and manufacturability.A seven-record-site neural probe was formed by inductive-coupled plasma(ICP) dry etching of an SOI substrate.The thickness of the probe is 15 μm.The shaft of the probe has dimensions of 3 mm×100 μm×15 μm with typical area of the record site of 78.5 μm2.The im...