SMP技术与SMP服务器

本文简要介绍了ＳＭＰ技术及其在曙光高性能ＳＭＰ系列服务器产品中的应用     

多处理器芯片体系结构研究

随着超大规模集成电路工艺和超级计算技术的发展，作者认为在单个芯片内集成多处理器系统将成为可能。本文详细讨论了多处理器芯片的分类和结构，着重阐述了同构型多处理器芯片的主要研究方向，并对同构型多处理器的可行性作出了分析。     

数字信号处理(DSP)器件综述

简述了DSP器件的发展和基本特征。对通用型和专用型DSP产品的现状和特点做了综述,简要分析了DSP产品今后的发展趋势。     

SIMIATIC S5多处理器在H型钢厂的应用

马钢Ｈ型钢厂的ＰＬＣ系统中采用了先进的多处理器技术，扩大了ＰＬＣ执行用户程序的容量，提高了运行速度。文中介绍了多处理方式的作用，软件条件和分析方法。     

利用冗余核的MPSoC故障检测方法

在处理器可靠性研究中,为在容错机制部署与容错开销之间达到较好的平衡,提出一个利用冗余核进行检测代码计算任务的多处理器片上系统(MPSoC)故障检测方法。该方法利用多核系统天然的冗余特性,将用于进行故障检测的冗余代码中的大部分计算任务转移到冗余核中进行,检测软件控制流的正确性和数据的一致性,实现MPSoC的故障检测。所提方法无需添加额外硬件,通过指令级的冗余进行故障检测,可满足系统可靠性需求,同时又能减少面积开销,在性能方面和花销上做到有效的权衡。在一个MPSoC上对所提方法进行验证实验,通过故障注入,运行多个基准程序进行有效性验证,并将所提方法与几种具有代表性的软件检测硬件故障方法故障检测能力、面积、内存以及性能花销等方面进行比较,实验结果证明所提方法有效且能够在性能和花销之间取得较好的权衡。     

Index-Based Cache Coherence Protocol

A multiprocessor envirorLment may encounter many problems such as deadlock, load balancing and cache coherence. However, the latter is considered the most dangerous if not properly designed, the system works naturally but generates inaccurate results. This occurs if obsolete versions of a memory block are used. Users may not be aware of the presence of such problem. Two main approaches are known to maintain data consistency： namely, snoopy and directory-based protocols. Each approach has its advantages and limitations. This paper proposes a new technique that considers both previously mentioned approaches. The network architecture is slightly updated by adding an index table to each processor. The proposed protocol is expected to reduce the access time, decrease the number of accesses to main memory, maintain data consistency, and assure the usage of the most recent value of a shared variable.     

A new parallel lattice reduction algorithm for BKZ reduced bases

In order to implement the original BKZ algorithm in parallel,we describe it in terms of parallelism and give its parallel implementation scheme.Then we analyze the efficiency of algorithm’s parallel implementation and show that the speedup factor of BKZ algorithm in parallel is extremely low.Therefore we present a new parallel lattice reduction algorithm suitable for multiprocessor computer architecture.The new algorithm can obtain a BKZ reduced basis and the parallel speedup is effective.Also with the practical results,although the computational complexity increases compared with the original BKZ algorithm,we still indicate that the new algorithm performs well in parallel and the time cost in parallel is less.At the same time,we show that the length of the shortest vector is smaller.