离散Hopfield神经网络和联想记忆的开关电流技术实现

研究了离散Ｈｏｐｆｉｅｌｄ神经网络（ＤＨＮＮ）和联想记忆神经网络的开关电流技术实现，利用多权输入跨导，开关电流延迟器（ＳＩＤ）和可编程电流比较器（ＰＣＣ）实现了离散Ｈｏｐｉｅｌｄ神经网络，并提出了利用离散Ｈｏｐｆｉｅｌｄ神经网络实现自联想记忆时相应的开关电流电路，所提出了开关电流神经网络适宜于超大规模集成，能在低电压（如３．３Ｖ）下工作。     

基于约束优化的联想记忆模型学习算法

本文提出了一种对称互连神经元网络的学习策略,利用全局约束优化方法确定连接权。优化过程采用了梯度下降技术。这种学习算法可以保证训练样本成为系统的稳定吸引子,并且具有优化意义上的最大吸引域。本文讨论了网络的存储容量,训练样本的渐近稳定性和吸引域大小。计算机实验结果说明了学习算法的优越性。     

LS SIMD微处理器中的三组指令并发执行的设计

文章介绍了LS SIMD微处理器中实现三组指令并发执行的可能性和必要性，分析了三组指令并发执行给流水线带来的影响，并讨论了控制逻辑对三级指令并发执行的控制及其实现形式。     

Liquid Crystal Television Spatial Light Modulator

The liquid crystal televison spatia light modulator(LCTVSLM)characterized is usable in optical processing applications.e.g.,optical pattern recognition,associative memory,optical computing,correlation detection and optical data processing systems.The array performance and real-time optical correlation applications are reviewed.     

一种低成本128位高精度浮点SIMD乘加单元的设计与实现

SIMD单元集成已经成为提高处理器性能的重要途径之一。虽然定点SIMD单元的硬件复用低成本设计技术已经较为成熟,但是,大部分浮点SIMD单元的硬件设计还停留在简单的硬件复制方法上。本文针对日益增长的128位高精度浮点操作的计算需求,提出了其相应的SIMD低成本硬件结构方案。综合实验结果表明,所提出的SIMD浮点乘加单元比传统128位高精度浮点乘加单元具有更加优化的性能与面积参数。     

FT-SIMD:一种高性能乘法器的设计

为了提高多媒体数据的处理能力,高性能DSP普遍引入了SIMD技术。作为DSP重要组成部分的乘法器也必须具备这一功能。本文对SIMD乘法器的实现进行深入研究,提出了一种新的SIMD乘法器体系结构,采用两个16×8乘法器,通过对其操作数和结果进行符号扩展和拼接等处理,简单而高效地实现了16位FT-SIMD乘法器。同时,本体系结构可以扩展为32位和64位的SIMD乘法器。     

PRAND: GPU accelerated parallel random number generation library: Using most reliable algorithms and applying parallelism of modern GPUs and CPUs

The library PRAND for pseudorandom number generation for modern CPUs and GPUs is presented. It contains both single-threaded and multi-threaded realizations of a number of modern and most reliable generators recently proposed and studied in Barash (2011), Matsumoto and Tishimura (1998), L’Ecuyer (1999,1999), Barash and Shchur (2006) and the efficient SIMD realizations proposed in Barash and Shchur (2011). One of the useful features for using PRAND in parallel simulations is the ability to initialize up to 10¹⁹${10}^{19}$ independent streams. Using massive parallelism of modern GPUs and SIMD parallelism of modern CPUs substantially improves performance of the generators.     

Novel associative classifier based on dynamic adaptive PSO: Application to determining candidates for thoracic surgery

Association rule mining is a data mining technique for discovering useful and novel patterns or relationships from databases. These rules are simple to infer and intuitive and can be easily used for classification in any domain that requires explanation for and investigation into how the classification works. Examples of such areas are medicine, agriculture, education, etc. For such a system to find wide adoptability, it should give output that is correct and comprehensible. The amount of data has been growing very fast and so has the search space of these problems. So we need to change traditional methods. This paper discusses a rule mining classifier called DA-AC (dynamic adaptive-associative classifier) which is based on a Dynamic Particle Swarm Optimizer. Due to its seeding method, exemplar selection, adaptive parameters, dynamic reconstruction of regions and velocity update, it avoids premature convergence and provides a better value in every dimension. Quality evaluation is done both for individual rules as well as entire rulesets. Experiments were conducted over fifteen benchmark datasets to evaluate performance of proposed algorithm in comparison with six other state-of-the-art non associative classifiers and eight associative classifiers. Results demonstrate competitive performance of proposed DA-AC while considering predictive accuracy and number of mined patterns as parameters. The method was then applied to predict life expectancy of post operative thoracic surgery patients.     

Improved GPU SIMD control flow efficiency via hybrid warp size mechanism

High single instruction multiple data (SIMD) efficiency and low power consumption have made graphic processing units (GPUs) an ideal platform for many complex computational applications. Thousands of threads can be created by programmers and grouped into fixed-size SIMD batches, known as warps. High throughput is then achieved by concurrently executing such warps with minimal control overhead. However, if a branch instruction occurs, which assigns different paths to different threads, one warp will be broken into multiple warps that have to be executed serially, consequently reducing the efficiency advantage of SIMD. In this paper, the contemporary fixed-size warp design is abandoned for a hybrid warp size (HWS) mechanism. Mixed-size warps are generated according to HWS and are scheduled and issued flexibly. The simulation results show that this mechanism yields an average speedup of 1.20 over the baseline architecture for a wide variety of general purpose GPU applications. The paper also integrates HWS with dynamic warp formation (DWF), which is a well-known branch handling mechanism used to improve SIMD utilization by forming new warps out of split warps in real time. The simulation results show that the combination of DWF and HWS generates an average speedup of 1.27 over the DWF-only platform with an estimated area increase of about 1% of DWF.