A novel low power hybrid cache using GC-EDRAM cells

In a typical embedded CPU, large on-chip storage is critical to meet high performance requirements. However, the fast increasing size of the on-chip storage based on traditional SRAM cells makes the area cost and energy consumption unsustainable for future embedded applications. Replacing SRAM with DRAM on the CPU’s chip is generally considered not worthwhile because DRAM is not compatible with the common CMOS logic and requires additional processing steps beyond what is required for CMOS. However a special DRAM technology, Gain-Cell embedded-DRAM (GC-eDRAM)  [1], [2], [3] is logic compatible and retains some of the good properties of DRAM (small and low power). In this paper we evaluate the performance of a novel hybrid cache memory where the data array, generally populated with SRAM cells, is replaced with GC-eDRAM cells while the tag array continues to use SRAM cells. Our evaluation of this cache demonstrates that, compared to the conventional SRAM-based designs, our novel architecture exhibits comparable performance with less energy consumption and smaller silicon area, enabling the sustainable on-chip storage scaling for future embedded CPUs.     

新一代IP QoS的实现

文章介绍了新一代IP骨干网上的IP QoS实现技术，论述了集成业务(IntServ)与差分业务(DiffServ)解决方案的特点，详细介绍了相关的队列管理与排队机制。并结合多协议标签交换（MPLS)技术的最新发展，阐述了综合多协议标签交换流量工程与DiffServ技术体系端到端IP QoS的实现。     

USERS' TWO-DIMENSIONAL INTEREST AND ITS STORAGE METHOD

The users' interest can be mined from the web cache and can be used widely. The interest can be specialized by the two-tuple (term, weight) in the simple interest model, in which the association relations are not mined, and then the interest cannot be associated in expressing the users' interest. Based on analyzing the WWW cache model, this letter brings forward a two-dimensional interest model and gives the interrelated methods on how to store the two-dimensional interest model effectively.     

USERS’ TWO-DIMENSIONAL INTEREST AND ITS STORAGE METHOD

The users‘ interest can be mined from the web cache and can be used widely.The interest can be specialized by the two-tuple(term,weight) in the simple interest model,in which the association relations are not mined.and then interest cannot be associated in expressing the users‘interest.Based on analyzing the WWW cache model,this letter brings forward a twodimensional interest model and gives the interrelated methods on how to store the two-dimensional interest model effectively.     

流媒体技术驱动宽带网应用

流媒体技术是宽带网应用的支撑技术，在宽带建设中应用是最关键的，文章从宽带网建设的困惑谈起，详细介绍了流媒体技术的原理、实现方法，最后谈到世界上3家主流公司流媒体产品的基本情况。     

Measuring consistency in TTL-based caches

We propose a general modeling framework to evaluate the performance of cache consistency algorithms. In addition to the usual hit rate, we introduce the hit^* rate as a consistency measure, which captures the fraction of non-stale downloads from the cache. We apply these ideas to the analysis of the fixed TTL consistency algorithm in the presence of network delays. The hit and hit^* rates are evaluated when requests and updates are modeled by renewal processes. Classical results on the renewal function lead to various bounds.     

TCP/IP网络的动态模型描述

拥塞现象成为TCP/IP网络发展面临的一个重要问题。因此，拥塞控制对TCP/IP网络的鲁棒性和稳定性具有重要作用。目前，网络拥塞控制策略主要包括两类：端到端的控制机制，如TCP拥塞控制算法；网络内部的主动队列管理(AQM)策略。但由于缺乏对网络系统动态特性的了解，这些拥塞控制策略大都基于专家经验，并没有建立完整的理论分析框架。为此，本文从数据流的角度出发，通过建立网络基本单元状态方程模型来实现IP网络系统的数学解析模型，然后用混杂系统来描述TCP带有拥塞控制策略的数据传输过程，建立了TCP/IP网络的动态模型，为网络系统中动态性能的分析、拥塞控制策略的设计奠定了基础。实验结果表明，该数学模型与NS仿真实验的结果相一致。     

改善磁盘阵列性能的方法

磁盘阵列是解决计算机Ｉ／Ｏ瓶颈问题的有效方法之一，通过对现有磁盘阵列结构的研究，提出了４种改善磁盘阵列性能的方法，即良分利用磁盘带宽，平衡多盘的负载，减少奇偶检验数据存取时间和磁盘阵列Ｃａｃｈｅ技术等，分析结果表明：在事务处理应用领域，利用Ｃａｃｈｅ来把小写转化为大写可大大改善目前一般情况下，以一道数据大小来作为磁盘的基本存取大小是合适的选择，磁盘阵列负载平衡设计不足是指正常模式下系统请求在多盘间     

Putting it all together – Formal verification of the VAMP

In the verified architecture microprocessor (VAMP) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA. A shorter version of this article with the title “Instantiating uninterpreted functional units and memory system: functional verification of the VAMP” appeared in [8]. The work reported here was done while all the authors were with Saarland University.     

Jitter in ATM networks and its impact on peak rate enforcement

Cells arriving to an ATM network experience random delays due to queueing in upstream multiplexing stages, notably in customer premises. This is the phenomenon of jitter and the aim of the present paper is to study its influence on peak rate enforcement. We first introduce some general characterizations of jitter and then, describe two models of jittered flows based on simple queueing systems. We discuss the objectives of peak rate enforcement and study the impact of jitter on the dimensioning of jumping window and leaky bucket mechanisms. A useful synthetic characterization of jitter appears to be a remote quantile of the cell delay distribution expressed in units of the initial inter-cell interval.