钱宁生平和他的《泥沙运动力学》

本文简要介绍了钱宁从事泥沙研究事业的一生及其主要成就；对《泥沙运动力学》一书进行了评述，并分章扼要说明及主要内容。与此同时，说明了作者对泥沙研究一些问题的观点。     

RS(31,27)高速编译码器的FPGA实现

RS码是目前最有效、应用最广泛的差错控制编码方法之一.该文深入研究了RS编解码的原理,对相关算法进行优化.并在FPGA上实现了(31,27)编解码器.由仿真结果验证了该编解码器占用系统资源少,运行时间快,能够满足通信系统上的要求.     

基于FPGA的RS(255,239)编译码器

编码是一种具有较强纠错能力的多进制BCH编码,其既可纠正随机错误,又可纠正突发错误。RS编译码器广泛应用于通信和存储系统,为解决高速存储器中数据可靠性的问题,文中提出了RS编码的实现方法,并对编码进行了时序仿真。仿真结果表明,该译码器可实现良好的纠错功能。     

A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm

Reed-Solomon (RS) codes play an important role in providing error protection and data integrity. Among various Reed-Solomon decoding algorithms, the Peterson-Gorenstein-Zierler (PGZ) algorithm in general has the least computational complexity for small t values. However, unlike the iterative approaches (e.g., Berlekamp-Massey and Euclidean algorithms), it will encounter divided-by-zero problems in solving multiple t values. In this paper, we propose a multi-mode hardware architecture for error numbers ranging from zero to three. We first propose a cost-down technique to reduce the hardware complexity of a t = 3 decoder. A Finite-field Inversion (FFI) elimination scheme is also proposed in our PGZ kernel. Next, we perform an algorithmic-level derivation to identify the configurable feature of our design. With those manipulations, we are able to perform multi-mode RS decoding in one unified VLSI architecture with very simple control scheme. The very low cost and simple data-path make our design a good choice in small-footprint embedded VLSI systems such as Error Control Coding (ECC) in memory/storage systems.     

一种基于FPGA的RS编译码器设计与实现

RS码是线性分组码中具有很强纠错能力的多进制BCH码,其在纠正随机错误和突发错误方面非常有效,因此被广泛应用于通信和数据存储系统。本文提出了一种实现复杂度低、高效率的RS编译码器实现电路,包含RS编码器、Horner准则的伴随式计算、BM算法、Chien搜索等模块,以RS(15,9)为例运用VHDL在ISE14.6软件环境下进行了功能仿真,结果与Matlab得到的理论结果一致。该方法适用于任意长度的RS编码,有着重要的应用价值。     

一种高效RS编解码器的FPGA实现

提出了一种实现复杂度低、高效率的RS(204,188)编解码器的FPGA实现电路.整个FPGA设计分为RS编码器、Homer准则的伴随式计算、改进的BM算法、Chien搜索求根和Forney算法求差错幅值等5个模块,同时,总体电路采用了pipeline结构,有效提高了译码速率.选用Xilinx公司的Spartan3E系列XC3S500E芯片,译码时延242个时钟周期,使用FPGA资源186000门,译码性能与理论值一致,已用于特定无线图像传输系统.     

Complexity analysis of precipitation in changing environment in Chien River Basin,China

The hydrological processes influenced by the multiple factors of climate,geography,vegetation,and human activities are becoming more and more complex,which is an important characteristic of hydrological systems.The different complexity distributions of precipitation processes of the Chien River Basin (a sub-basin of the Minjiang Basin) in two periods (from 1952 to 1980,and from 1981 to 2009) are illustrated using the fractal based on the continuous wavelet transform (CWT).The results show that (1) at the basin scale the precipitation process in the latter period is more complex than in the former period;(2) the maximum value of the complexity distribution moved from the east to the middle;and (3) through analysis of the time-information and space-information concealed in this complexity change,the precipitation characteristics in the changing environment in the basin can be illuminated.This study could provide a reference for research on disaster pre-warning in changing environments and for integrated water resources management in the local basin.     

一种基于ME算法的RS译码器VLSI高速实现方法

针对ME算法VLSI结构进行了分析,提出ME算法的流水线及最小化VLSI结构,以满足数据处理速率不断提高的需求。并利用该算法实现结构设计了一种低资源占用率、低成本的高速RS译码器。逻辑综合及仿真结果表明,基于Altera公司CycloneII系列FPGA的RS(255,239)译码器,工作时钟达210 MHz,可满足数据速率1.68 Gb·s^-1的编译码要求。     

65nm工艺下面积功耗优化的BCH电路设计

在65 nm工艺下实现了最大纠正84 bit错误的带循环冗余码(CRC)校验保护功能的BCH(32767,16416)纠错电路,纠错能力可配置。该设计采用频率比为1∶4的两种工作时钟,最高工作频率为100 MHz和400 MHz。两种工作频率的合理组合降低译码运算的延迟,提高固态硬盘读写数据的性能,同时提供了分时复用的可能。通过复用伴随式计算、关键方程系数求解(iBM算法)和钱搜索过程中的有限域乘法运算单元优化芯片面积。通过调整钱搜索的起始位置,实现编码和伴随式计算的求余电路复用,实现面积和功耗的优化,最终芯片面积节省了27%,功耗降低了26%。     

RS(63,45)编译码器的设计与FPGA实现

里德-索罗门(RS)编码是一类具有很强纠错能力的多进制BCH编码,它不但可以纠正随机错误,也能纠正突发错误。首先介绍了伽罗华域加法器和乘法器的设计,然后详细地阐述了RS(63,45)编译码器各模块的设计原理。对编译码器各模块先用Matlab进行设计,验证设计的正确性,再对译码器模块进行纠错性能测试。时序仿真结果表明,该译码器能实现最大的纠错能力。设计的编译码器能运用到实际的无线通信系统中去。