A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol

We present a formal model of asynchronous communication between two digital hardware devices. The model takes the form of a function in the Boyer-Moore logic. The function transforms the signal stream generated by one processor into that consumed by an independently clocked processor, given the phases and rates of the two clocks and the communications delay. The model can be used quantitatively to derive concrete performance bounds on communications at ISO protocol level 1 (physical level). We use the model to show that an 18-bit/cell biphase mark protocol reliably sends messages of arbitrary length between two processors provided the ratio of the clock rates is within 5% of unity.     

A novel clock generation algorithm for system-on-chip based on least common multiple

Due to increase in the number of Intellectual Property (IP) cores, clock generation in current day System-on-Chips (SoCs) is facing a crisis. The conventional method of using a dedicated Phase Locked Loop (PLL) to generate the clock for each IP core is becoming inefficient in terms of power and cost. We propose an algorithm based on Least Common Multiple (LCM) to minimize the number of PLLs required to generate the clocks for the IP cores in a SoC. This is done by finding an Optimum Operating Frequency (OOF) for each IP core within 10% below the maximum operating frequency of the core. The OOF is chosen such that the LCM of the OOF of all the IP cores is minimized. Simulated annealing is used to find the LCM. This LCM is the crucial high frequency from which maximum number of clocks can be derived by clock dividers.     

SSI:一种IPv6/IPv4多址同源识别模型

IPv6/IPv4共存环境下多址同源识别是共存网络管理与拓扑发现的一个关键问题。现有研究主要集中于子网内部的双栈发现及单一IP协议栈中的别名解析,难以识别远程IPv6/IPv4共存网络中的多址同源。通过分析同源地址间的本质联系,提出一种IPv6/IPv4多址同源识别模型(SSI),该模型综合利用特殊地址格式匹配、TCP时钟指纹比对和上层协议短时致瘫等多种方式来提高同源地址的识别能力。实验结果表明,上述方法均可有效识别IPv6/IPv4多址同源;SSI模型具有较理想的识别率和正确率。     

路灯控制电路设计

该路灯控制系统主要由时钟发生电路、路灯控制电路、LCD显示电路、声光报警电路、键盘控制电路和单片机控制电路等部分组成。在时钟发生电路中,采用低功耗实时时钟电路芯片DS1302,它可以对年、月、日、周日、时、分、秒进行计时,计时后,经过单片机的控制处理后从显示屏上将计时的数据显示出来。而路灯控制部分通过对外部环境进行检测,实现不同环境的不同操作,从而实现各个不同功能。由于采用了较高级的时钟控制元件、精度较高的红外检测装置和外界光检测装置,实现了对外部环境的控制功能,而且有效地提高了精度。     

对一种公平非否认协议的新改进

Zhou-Gollmann协议是一种公平非否认协议,近年来得到广泛讨论.Kim发现该协议在时限公平性方面存在缺陷,针对该缺陷提出一种改进的协议,但其改进方法高度依赖于网络时钟的同步.通过详细分析,发现在缺乏时钟同步时Kim的改进协议也可导致不公平.针对此问题,提出一种新的改进方案.新的改进消除了协议对时钟同步的依赖性,保持了协议的公平非否认性,且不会降低协议的效率.     

The Asynchronous Bounded-Cycle model

This paper shows how synchrony conditions can be added to the purely asynchronous model in a way that avoids any reference to message delays and computing step times, as well as system-wide constraints on execution patterns and network topology. Our Asynchronous Bounded-Cycle (ABC) model just bounds the ratio of the number of forward- and backward-oriented messages in certain (“relevant”) cycles in the space-time diagram of an asynchronous execution. We show that clock synchronization and lock-step rounds can be implemented and proved correct in the ABC model, even in the presence of Byzantine failures. Furthermore, we prove that any algorithm working correctly in the partially synchronous Θ-Model also works correctly in the ABC model. In our proof, we first apply a novel method for assigning certain message delays to asynchronous executions, which is based on a variant of Farkas’ theorem of linear inequalities and a non-standard cycle space of graphs. Using methods from point-set topology, we then prove that the existence of this delay assignment implies model indistinguishability for time-free safety and liveness properties. We also introduce several weaker variants of the ABC model, and relate our model to the existing partially synchronous system models, in particular, the classic models of Dwork, Lynch and Stockmayer and the query-response model by Mostefaoui, Mourgaya, and Raynal. Finally, we discuss some aspects of the ABC model’s applicability in real systems, in particular, in the context of VLSI Systems-on-Chip.     

Assessing two new wearable input paradigms: The Finger-Joint-Gesture palm-keypad glove and the invisible phone clock

Text and digit entry speed of two wearable one-handed input paradigms, the Finger-Joint-Gesture palm-keypad glove and the Invisible Phone Clock, were benchmarked against traditional one-handed cellular phone keypad input in a repeated-measurement design employing 18 subjects using a 9-word sentence. No significant difference in error-corrected text entry speed (5.3 ec-wpm) was found. Digit entry speed was significantly faster (8.3 ec-wpm) and differed significantly between input paradigms. Furthermore, digit entry was fastest for the traditional cellular phone keypad and slowest for the Invisible Clock keypad. A prediction model based on Fitts' law slightly overestimated text entry speed for novice users. Another prediction model, where each movement time between successive keys was corrected for key repeat time for each specific input paradigm, predicted the experimental results more accurately. Thirteen of the subjects ranked the Invisible Phone Clock as 1^st choice. The subjects' mapping of the Ericsson cellular phone functions (YES, CLR, NO, <,> and Address Book) was not according to the designer's model, partly due to functional fixedness. The input paradigms could be suitable candidates for new fragmentised interfaces where wearability is the key issue.     

Analysis of a clock synchronization protocol for wireless sensor networks

The Dutch company Chess develops a wireless sensor network (WSN) platform using an epidemic communication model. One of the greatest challenges in the design is to find suitable mechanisms for clock synchronization. In this paper, we study a proposed clock synchronization protocol for the Chess platform. First, we model the protocol as a network of timed automata and verify various instances using the Uppaal model checker. Next, we present a full parametric analysis of the protocol for the special case of cliques (networks with full connectivity), that is, we give constraints on the parameters that are both necessary and sufficient for correctness. These results have been checked using the proof assistant Isabelle. We report on the exhaustive analysis of the protocol for networks with four nodes, and we present a negative result for the special case of line topologies: for any instantiation of the parameters, the protocol will eventually fail if the network grows.     

一套用于激光多步共振电离截面测量的多定标数据获取系统

本文主要介绍了一套应用于激光多步共振电离截面测量的CAMAC多定标数据获取系统.它可以实现严格同步采集多个实验参数,并能灵活适应实验条件的宽范围变化.CAMAC前端的定标器数目可通过更改数据读出表文件来任意增减;获取方式分为自动重复获取和手动单次获取;获取时间单位可在1ms-800s范围内调节.经过测试得到,本数据获取系统的获取时间单位选择100s时长时间工作的稳定性(△t/t)好于±0.01%,充分证实了该套数据获取系统长时间在线采集实验数据的可靠性.最后利用这套系统同步测量了三台热电偶激光功率探头的功率-响应时间曲线.     

高速系统PCB设计中的几个关键问题

随着微电子技术的飞速发展，高速大规模集成电路的广泛应用，高速系统的设计也越来越受到重视，高速系统与低速系统的PCB设计有很大不同。本文从实际设计的角度介绍了高速系统中电源、接地、时钟电路、过孔等的设计和需要注意的问题。