A bandwidth latency tradeoff for broadcast and reduction

The “fractional tree” algorithm for broadcasting and reduction is introduced. Its communication pattern interpolates between two well known patterns—sequential pipeline and pipelined binary tree. The speedup over the best of these simple methods can approach two for large systems and messages of intermediate size. For networks which are not very densely connected the new algorithm seems to be the best known method for the important case that each processor has only a single (possibly bidirectional) channel into the communication network.     

基于多跳间时延协作的最久分组优先算法

提出了一种基于多跳间时延协作的Crossbar调度算法。该算法以分组头中记录的时延为权重对分组进行调度,通过控制分组在各跳上的时延来达到调节端到端时延的目的。算法还使路由器避免了维护每个流的状态信息以及对单个流进行的复杂的队列管理和调度。计算机仿真表明,算法具有较高的资源利用率、较低的端到端时延抖动和较低的分组丢弃率等特点。     

一种支持单播与组播混合业务的高速Crossbar调度算法

当前在高速crossbar中支持单、组播混合业务调度的实用算法一般采用请求-许可-接受的处理流程(例如ESLIP算法)。研究发现,该类算法中存在单、组播许可相互阻塞现象,造成调度效率降低。从实用性出发,该文提出了一种新的支持单、组播混合业务的调度算法ERGRR(Extended Request-Grant-based Round- Robin),通过简化调度处理流程,克服了许可阻塞现象,提高了系统吞吐量、时延等性能。仿真结果表明,在单、组播混合业务流下,ERGRR算法吞吐量、时延等性能优于ESLIP算法。另外,ERGRR算法具有更好的公平性以及更加易于硬件实现。     

BYS91─1多机系统存储器频带的分析

ＢＹＳ９１－１是基于ＲＩＳＣｉ８６０ＸＰ设计的具有局部存储和共享存储的多机系统。本文以排队论为工具，建立了该系统存储器的排队模型，给出了存储器使用频带的解析式，并结合具体的设计参数，分析了系统中处理机个数、存储空间配置对存储器有效频带的影响。     

一种支持多优先级的高速Crossbar调度算法

现有支持多优先级的高速Crossbar调度算法需要交互的控制信息较多,控制信息的传输时间已成为调度算法性能提高的主要瓶颈.为提高Crossbar调度的性能,本文提出一种新的支持多优先级的高速Crossbar调度算法p-iDRR,该算法具有硬件实现简单、控制信息量少、高速和可扩展性强等优点.仿真结果表明,p-iDRR具有良好的吞吐量、时延性能,适用于高速、多端口、大容量的路由器.     

The optical crossbar switch for signal routeing on board communication satellites

A switch matrix operating on baseband or microwave signals is a critical element of communications satellites employing multiple beam antennas and on-board switching. Optical switching by spatial light modulators (SLMs) offers a means of implementing large and highly flexible switch arrays capable of routeing signals at baseband or microwave frequencies. This approach offers potential mass, power and size advantages compared to alternative technologies. The paper reviews the essential features of optical crossbar switch architectures based on SLMs and discusses options for the lasers, SLMs, interface optics and photodetectors. Proof-of-concept demonstrators for optical crossbar switches operating on both baseband and microwave signals are described. Finally, an outline design for a compact switch module is described and the critical component developments needed to realize this are identified.     

Hardware system of the Earth Simulator

The Earth Simulator (ES), developed under the Japanese government’s initiative “Earth Simulator project”, is a highly parallel vector supercomputer system. In this paper, an overview of ES, its architectural features, hardware technology and the result of performance evaluation are described.

In May 2002, the ES was acknowledged to be the most powerful computer in the world: 35.86 teraflop/s for the LINPACK HPC benchmark and 26.58 teraflop/s for an atmospheric general circulation code (AFES). Such a remarkable performance may be attributed to the following three architectural features; vector processor, shared-memory and high-bandwidth non-blocking interconnection crossbar network.

The ES consists of 640 processor nodes (PN) and an interconnection network (IN), which are housed in 320 PN cabinets and 65 IN cabinets. The ES is installed in a specially designed building, 65 m long, 50 m wide and 17 m high. In order to accomplish this advanced system, many kinds of hardware technologies have been developed, such as a high-density and high-frequency LSI, a high-frequency signal transmission, a high-density packaging, and a high-efficiency cooling and power supply system with low noise so as to reduce whole volume of the ES and total power consumption.

For highly parallel processing, a special synchronization means connecting all nodes, Global Barrier Counter (GBC), has been introduced.     

On the speedup required for combined input- and output-queued switching

Architectures based on a non-blocking fabric, such as a crosspoint switch, are attractive for use in high-speed LAN switches, IP routers, and ATM switches. When operating at the highest speed, memory bandwidth limitations dictate that queues be placed at the input of the switch. But it is well known that input-queueing can lead to low throughput, and does not allow the control of latency through the switch. This is in contrast to output-queueing which maximizes throughput and permits the accurate control of packet latency through scheduling. We ask the question: Can a switch with combined input and output queueing be designed to behave identically to an output-queued switch? In this paper, we prove that if the switch uses virtual output queueing and has an internal speedup of just four, it is possible for it to behave identically to an output-queued switch, regardless of the nature of the arriving traffic. Our proof is based on a novel scheduling algorithm, called Most Urgent Cell First. We find that with a speedup of four the most urgent cell first algorithm (or MUCFA) enables perfect emulation of a FIFO output-queued switch, i.e. one in which packets depart in the same order that they arrived. We extend this result to show that with a small modification, the MUCFA algorithm enables perfect emulation of a variety of output scheduling policies, including strict priorities and weighted fair-queueing. This result makes possible switches that perform as if they were output-queued, yet use memories that run more slowly.     

光开关矩阵中Crossbar光交换网络的研究

针对DWDM光网络光交叉连接中光开关矩阵对其光交换网络的要求,分析了目前常用的置换型和常规型Crossbar光交换网络的性能,提出了一种新型的寻径型Crossbar光交换网络及其光学实现方法.该新方法利用1×2和2×1光开关构造寻径扇出和寻径扇入网络,具有严格无阻塞性,插损低,并可实现对光信号卸载,适用于中等规模的光开关矩阵.     

Control of filament size and reduction of reset current below 10 μA in NiO resistance switching memories

Resistive-switching memory (RRAM) is receiving a growing deal of research interest as a possible solution for high-density, 3D nonvolatile memory technology. One of the main obstacle toward size reduction of the memory cell and its scaling is the typically large current I_reset needed for the reset operation. In fact, a large I_reset negatively impacts the scaling possibilities of the select diode in a cross-bar array structure. Reducing I_reset is therefore mandatory for the development of high-density RRAM arrays. This work addresses the reduction of I_reset in NiO-based RRAM by control of the filament size in 1 transistor-1 resistor (1T1R) cell devices. I_reset is demonstrated to be scalable and controllable below 10 μA. The significance of these results for the future scaling of diode-selected cross-bar arrays is finally discussed.