Adaptive GLR-, Rao- and Wald-based CFAR detectors for a subspace signal embedded in structured Gaussian interference

The problem of detecting a subspace signal embedded in subspace Gaussian interference and thermal noise is studied in this paper. In this problem, both the signal-independent and signal-dependent interferences are assumed to be present, therefore the overall interference subspace covers the signal subspace. The approach of this paper extends previous works involving either of those two kinds of interferences. A set of secondary data containing only interference plus noise is employed to estimate the interference covariance matrix and the noise power. Three new detectors are designed via the generalized likelihood ratio (GLR), Rao and Wald tests, respectively. Their probabilities of false alarms (PFAs) and detections are analytically derived. The PFAs show that the new detectors have the constant false alarm rate (CFAR) property against the interference and noise. Numerical results show that the new detectors outperform their counterparts for the studied problem. Furthermore, the new detectors are less sensitive to the secondary data size and to the mismatched subspace signal than some other detectors, such as the GLR detector (GLRD), the adaptive matched filter (AMF), the adaptive subspace detector (ASD), etc.     

钢管套筒灌浆连接轴向受拉性能模拟试验研究

为研究钢管套筒灌浆连接轴向受拉破坏过程及破坏机理，试验中设计了16组48个钢管套筒灌浆连接试件，试件采用钢板代替圆钢管，并进行静载试验。分析了灌浆料裂缝扩展过程、荷载-相对位移曲线，并对抗剪键高距比、灌浆料厚度、侧向力等因素对破坏过程及承载力的影响进行分析。结果表明：对于不设置抗剪键的套筒灌浆连接试件，斜裂缝随机产生，裂缝分布不均匀；对于设置抗剪键的套筒灌浆连接试件，裂缝首先出现在底部抗剪键位置处，与水平方向夹角约为30°，随后在中部和上部抗剪键位置处分别出现斜裂缝。由于每个抗剪键上荷载分担并不均匀，与抗剪键接触的灌浆料逐渐达到极限压应力，达到极限状态时，承载力全部由抗剪键间的机械咬合力承担，在连接承载力中，可忽略摩擦力和胶结力作用。随着抗剪键高距比h/s增大，各试件初始剪切刚度相差不大，承载力增大，但增幅逐渐减小，建议抗剪键高距比0.06g/s>0.3，同时需要满足灌浆料灌注的施工要求。     

使用FPGA与SDRAM实现液晶显示控制模块的浅析

针对液晶显示控制板上存储器(SRAM)存储量小和频率低的情况,提出了基于DDR sdram作为显示存储器的LCD显示控制器的设计。使用了灵活性与可靠性高的现场可编程门阵列(FPGA)来实现各模块的逻辑功能,分析了实现LCD显示屏控制模块的方案。     

仙游抽水蓄能电站尾水系统充排水试验

为检查工程质量,查找输水系统可能存在的问题并消除隐患,保障电站安全运行,福建仙游抽水蓄能电站在投产发电前,要对输水发电系统进行充水试验与放空排水试验,在试验过程中监测输水系统的应力、应变与渗漏水情况。本文以尾水系统为例,介绍了试验所应具备的工程条件、工作程序及技术要求、试验成果分析和存在问题处理等。试验表明,仙游抽水蓄能电站尾水系统设计合理,施工质量优良,结构可靠,可供同类工程参考与借鉴。     

Combined hardware–software multi-parallel prefiltering on the Convey HC-1 for fast homology detection

Protein databases used in research are huge and still grow at a fast pace. Many comparisons need to be done when searching similar (homologous) sequences for a given query sequence in these databases. Comparing a query sequence against all sequences of a huge database using the well-known Smith–Waterman algorithm is very time-consuming. Hidden Markov Models pose an opportunity for reducing the number of entries of a database and also enable to find distantly homologous sequences. Fewer entries are achieved by clustering similar sequences in a Hidden Markov Model. Such an approach is used by the bioinformatics tool HHblits. To further reduce the runtime, HHblits uses two-level prefiltering to reduce the number of time-consuming Viterbi comparisons. Still, prefiltering is very time-consuming. Highly parallel architectures and huge bandwidth are required for processing and transferring the massive amounts of data. In this article, we present an approach exploiting the reconfigurable, hybrid computer architecture Convey HC-1 for migrating the most time-consuming part. The Convey HC-1 with four FPGAs and high memory bandwidth of up to 76.8 GB/s serves as the platform of choice. Other bioinformatics applications have already been successfully supported by the HC-1. Limited by FPGA size only, we present a design that calculates four first-level prefiltering scores per FPGA concurrently, i.e. 16 calculations in total. This score calculation for the query profile against database sequences is done by a modified Smith–Waterman scheme that is internally parallelized 128 times in contrast to the original Streaming ‘Single Instruction Multiple Data (SIMD)’ Extensions (SSE)-supported implementation where only 16-fold parallelism can be exploited and where memory bandwidth poses the limiting factor. Preloading the query profile, we are able to transform the memory-bound implementation to a compute- and resource-bound FPGA design. We tightly integrated the FPGA-based coprocessor into the hybrid computing system by employing task-parallelism for the two-level prefiltering. Despite much lower clock rates, the FPGAs outperform SSE-based execution for the calculation of the prefiltering scores by a factor of 7.9.     

机载光电雷达它机试飞技术研究

机载光电雷达受平台及大气环境影响较大,而它机试飞能有效规避研制风险,是产品研制的必经阶段。本文介绍了机载光电雷达它机试飞试验系统组成、试验流程和数据处理等内容。经工程验证,实施过程满足任务需求,对其他光电系统的它机及本机试飞具有参考价值。     

The World robot summit disaster robotics category – achievements of the 2018 preliminary competition

The World Robot Summit is a robot Olympics and aims to be held in a different country every four years from 2020. The concept of the Plant Disaster Prevention challenge is daily inspections, checks, and emergency response in industrial plants, and in this competition, robots must carry out these types of missions in a mock-up plant. The concept of the Tunnel Disaster Response and Recovery challenge is emergency response to tunnel disasters, and is a simulation competition whereby teams compete to show their ability to deal with disasters, by collecting information and removing debris. The Standard Disaster Robotics challenge assesses, in the form of a contest, the standard performance levels of a robot that are necessary for disaster prevention and emergency response. The World Robot Summit Preliminary Competition was held at Tokyo Big Sight in October 2018, and 36 teams participated in the Disaster Robotics Category. UGVs and UAVs contended the merits of new technology for solving complex problems, using core technologies such as mobility, sensing, recognition, performing operations, human interface, autonomous intelligence etc., as well as system integration and implementation of strategies for completing missions, gaining high-level results.     

A scalable architecture for geometric correction of multi-projector display systems

Multi-projector displays allow the realization of large and immersive projection environments by allowing the tiling of projections from multiple projectors. Such tiled displays require real time geometrical warping of the content that is being projected from each projector. This geometrical warping is a computationally intensive operation and is typically applied using high-end graphics processing units (GPUs) that are able to process a defined number of projector channels. Furthermore, this limits the applicability of such multi-projector display systems only to the content that is being generated using desktop based systems. In this paper we propose a platform independent FPGA based scalable hardware architecture for geometric correction of projected content that allows addition of each projector channel at a fractional increase in logic area. The proposed scheme provides real time correction of HD quality video streams and thus enables the use of this technology for embedded and standalone devices.     

基于学生群体心理测试系统的设计

心理测试的根本目的是为了让人们在测试过程中，产生某些特定行为，即个体对测试题目的反应，并根据这些行为反应来推论其相应的心理特性。在一定程度上帮助我们了解人类的心理活动，并从中得到帮助。因此，本文对基于学生群体心理测试系统的设计进行深入研究。