Reconfigurable hardware implementation of a phase-correlation stereoalgorithm

This paper describes the implementation of a stereo-vision system using Field Programmable Gate Arrays (FPGAs). Reconfigurable hardware, including FPGAs, is an attractive platform for implementing vision algorithms due to its ability to exploit parallelism often found in these algorithms, and due to the speed with which applications can be developed as compared to hardware. The system outputs 8-bit, subpixel disparity estimates for 256× 360 pixel images at 30,fps. A local-weighted phase correlation algorithm for stereo disparity [Fleet, D. J.: {Int. Conf. Syst. Man Cybernetics 1:48–54 (1994)] is implemented. Despite the complexity of performing correlations on multiscale, multiorientation phase data, the system runs as much as 300 times faster in hardware than its software implementation. This paper describes the hardware platform used, the algorithm, and the issues encountered during its hardware implementation. Of particular interest is the implementation of multiscale, steerable filters, which are widely used in computer vision algorithms. Several trade-offs (reducing the number of filter orientations from three to two, using fixed-point computation, changing the location of one localized low-pass filter, and using L1 instead of L2 norms) were required to both fit the design into the available hardware and to achieve video-rate processing. Finally, results from the system are given both for synthetic data sets as well as several standard stereo-pair test images.     

基于可重构系统的时域划分技术的研究

可重构计算是一种介于ASIC和通用微处理器之间的新的提升计算机性能的方法,对于数字信号处理、流媒体技术、图像压缩、密码学、生物信息处理等计算密集型方面的应用,可重构计算技术可以发挥巨大的优势。基于具有较少重构时间的实时可编程逻辑器件(如FPGA)的用户可编程性,其可作为多种硬件资源使用。如果其配置信息可以迅速更改,则由逻辑器件实现的硬件功能也可实现迅速切换。硬件资源的大小是有限的,那些超过器件有效硬件资源的较大任务需要通过时域划分来解决。该文对可重构计算以及时域划分的定义、分类,国内外研究现状和常见的研究方法做了详细的描述,并综合分析了一系列时域划分算法并进行了相关比较。     

Superpipelined high-performance optical-flow computation architecture

Optical-flow computation is a well-known technique and there are important fields in which the application of this visual modality commands high interest. Nevertheless, most real-world applications require real-time processing, an issue which has only recently been addressed. Most real-time systems described to date use basic models which limit their applicability to generic tasks, especially when fast motion is presented or when subpixel motion resolution is required. Therefore, instead of implementing a complex optical-flow approach, we describe here a very high-frame-rate optical-flow processing system. Recent advances in image sensor technology make it possible nowadays to use high-frame-rate sensors to properly sample fast motion (i.e. as a low-motion scene), which makes a gradient-based approach one of the best options in terms of accuracy and consumption of resources for any real-time implementation. Taking advantage of the regular data flow of this kind of algorithm, our approach implements a novel superpipelined, fully parallelized architecture for optical-flow processing. The system is fully working and is organized into more than 70 pipeline stages, which achieve a data throughput of one pixel per clock cycle. This computing scheme is well suited to FPGA technology and VLSI implementation. The developed customized DSP architecture is capable of processing up to 170 frames per second at a resolution of 800 × 600 pixels. We discuss the advantages of high-frame-rate processing and justify the optical-flow model chosen for the implementation. We analyze this architecture, measure the system resource requirements using FPGA devices and finally evaluate the system’s performance and compare it with other approaches described in the literature.     

An efficient hardware implementation of the elliptic curve cryptographic processor over prime field,

Elliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest-Shamir-Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, . This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex-7 FPGA platform over 224-bit and 256-bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal-oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field and , respectively. This design provides better area-delay product and high throughput value in both FPGA and ASIC when compared with other designs.     

Allocation heuristics and defragmentation measures for reconfigurable systems management

A novel technique is proposed for the management of a 2D reconfigurable device in order to get true hardware multitasking. We use a Vertex List Set to keep track of the free area boundary. This structure contains the best candidate locations for the task, and several heuristics are proposed to select one of them, based in fragmentation and adjacency. A Look-Ahead heuristic that anticipates the next known event is also proposed. A metric is used to estimate the fragmentation status of the FPGA, based on the number of holes and their shape. Defragmentation measures are taken when needed.     

Parameterized High Throughput Function Evaluation for FPGAs

This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters, multipliers, and dividers. We discuss trade-offs involved between (1) full-lookup tables, (2) bipartite (lookup-add) units, (3) lookup-multiply units, (4) shift-and-add based CORDIC units, and (5) rational approximation. Our treatment mainly focuses on explaining method (3), and briefly covers the background of the other methods. For lookup-multiply units, we provide equations for estimating approximation errors and rounding errors which are used to parameterize the hardware units. The resources and performance of the resulting design can be estimated given the input parameters. A selection of the compared methods are implemented as part of the current PAM-Blox module generation environment. An example shows that the lookup-multiply unit produces competitive designs with data widths up to 20 bits when compared with shift-and-add based CORDIC units. Additionally, the lookup-multiply method or rational approximation can produce efficient designs for larger data widths when evaluating functions not supported by CORDIC.     

面向可重构系统的负载均衡低能耗调度算法

主要研究了基于多FPGAs部件的可重构系统高能耗问题。首先,对多FPGAs部件可重构系统的特征进行了建模,包括重构端口受限、资源受限及通信开销等建立了问题模型;接着,基于概率论与统计学的离散方差理论,采用负载均衡思想设计和实现了一种低能耗调度算法MLB。它的原理是通过计算各个FPGA部件的总能耗方差来引导负载的均衡分配。最后,通过模拟仿真实验,将提出的MLB算法分别与贪心算法和最新研究MFIT算法进行了比较,结果表明提出的算法复杂度低、运行速度快,不仅多节约了15%的能量,而且缩短了最大完成时间。     

一种模拟单粒子瞬态产生和测量方法

为了提高利用静态随机存取存储器(SRAM)型现场可编程门阵列(FPGA)评估集成电路单粒子瞬态(SET)的精度,在瞬态脉冲的产生方面以及瞬态脉冲在FPGA中的传播特性方面进行了研究。提出一种基于IDELAY2延迟元件的瞬态脉冲产生和测量方法,利用该方法可以连续产生和测量宽度增量为78ps的正脉冲(0-1-0)和负脉冲(1-0-1),同时在FPGA内部实现8种不同的门电路逻辑链,研究它们对瞬态脉冲宽度的影响。实验结果表明该瞬态脉冲产生和测量方法实现简单,可以在不改变电路布局布线的前提下,改变注入脉冲的宽度,且计算得到的理论脉冲宽度与实际测量的误差小于7%,同时8种不同的门电路逻辑链对瞬态脉冲宽度的影响和门类型以及脉冲类型有关,与初始输入瞬态脉冲宽度无关。     

Embryonics: A Bio-Inspired Cellular Architecture with Fault-Tolerant Properties

This paper details and expands the work on Embryonics, a recently proposed fault-tolerant cellular architecture with reconfiguration properties inspired by the ontogenetic development of multicellular systems. The design of a selector-based embryonic cell, its applications and the reliability models associated to different embryonic reconfiguration strategies are presented. It is noted that embryonic distributed systems possess, in the majority of cases, better reliability characteristics than equivalent centralised systems.     

Fine-grained parallel implementations for SWAMP+ Smith–Waterman alignment

More sensitive than heuristic methods for searching biological databases, the Smith–Waterman algorithm is widely used but has the drawback of a high quadratic running time. The faster approach extends Smith–Waterman using Associative Massive Parallelism (SWAMP+) for three different parallel architectures: ASsociative Computing (ASC), the ClearSpeed coprocessor, and the Convey Computer FPGA coprocessor. We show that parallel versions of Smith–Waterman can be successfully modified to produce multiple BLAST-like sub-alignments while maintaining the original precision. SWAMP+ combines parallelism and the novel extension producing multiple sub-alignments for pairwise comparisons.