基于FPGA的全局异步局部同步四相单轨握手协议实现

在常规FPGA中设计了基于LUT的异步状态保持单元,实现了全局异步局部同步系统的接口电路、时钟暂停电路,进一步完成四相单轨握手协议。基于Quartus软件的逻辑锁定技术,采用Verilog HDL进行行为描述,构建了无冒险C单元库。在Altera CycloneⅡEP2C35F672C6器件上,完成了GALS系统的时序仿真,证明了四相单轨握手的正确性。     

Concurrency in Synchronous Systems

In this paper we introduce the notion of weak endochrony, which extends to a synchronous setting the classical theory of Mazurkiewicz traces. The notion is useful in the synthesis of correct-by-construction communication protocols for globally asynchronous, locally synchronous (GALS) systems. The independence between various computations can be exploited here to provide communication schemes that do not restrict concurrency while still guaranteeing correctness. Such communication schemes are then lighter and more flexible than their latency-insensitive or endo/isochronous counterparts. Work supported by the ARTIST and COLUMBUS IST European projects     

Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits

We consider the problem of synthesizing the asynchronous wrappers and glue logic needed for the correct GALS implementation of a modular synchronous system. Our approach is based on the weakly endochronous synchronous model, which defines high-level, implementation-independent conditions guaranteeing correct desynchronization at the level of the abstract synchronous model. We can therefore factor the synthesis problem into (1) a high-level, implementation-independent phase insuring the weak endochrony of each synchronous module and (2) the actual wrapper synthesis phase, highly simplified by the high-level assumptions, yet flexible enough to produce various, efficient implementations.We focus here on the synthesis of delay-insensitive asynchronous wrappers from weakly endochronous synchronous modules, and show how this can be done for a simple DLX processor model.     

A Survey of Desynchronization in a Polychronous Model of Computation

The synchronous hypothesis arose in the late Eighties as a conceptual framework for the computer-aided design of embedded systems. Along with this framework, the issue of desynchronization was simultaneously raised as the major topic of mapping the ideal communication and computation model of synchrony on realistic and distributed computer architectures.The aim of the present article is to survey the development of this topics in the particular yet promising model of one of the prominent environments that were build along these principles: Signal and its polychronous (synchronous multi-clocked) model of computation, before to give some hints and ideas about ongoing research addressing this issue.     

Scan Test Strategy for Asynchronous-Synchronous Interfaces

In the coming years, the well-known synchronous design style will not be able to keep pace with the increase speed and capabilities of integration of advanced processes. New design paradigms, like core reuse of the already designed synchronous modules and asynchronous designs, are considered in order to cope with the ever increasing complexity. The future SoCs will contain multiple synchronous and asynchronous cores. Asynchronous design will become more and more common among digital designers, while synchronous-asynchronous interactions will emerge as a key issue in the future SoC designs.This paper will present test strategies for 2-phase asynchronous-synchronous interfaces and vice versa. It will be shown how test vectors can be automatically generated using commercially available ATPG tools. The generated ATPG vectors will be able to test all stuck-at-faults within the asynchronous-synchronous interfaces.     

Generalized Artificial Life Structure for Time-dependent Problems

In recent years, more attention has been paid on artificial life researches. Artificial life(AL) is a research on regulating gene parameters of digital organisms under complicated problematic environments through natural selections and evolutions to achieve the final emergence of intelligence. Most recent studies focused on solving certain real problems by artificial life methods, yet without much address on the AL life basic mechanism. The real problems are often very complicated, and the proposed methods sometimes seem too simple to handle those problems. This study proposed a new approach in AL research, named "generalized artificial life structure(GALS)", in which the traditional "gene bits" in genetic algorithms is first replaced by "gene parameters", which could appear anywhere in GALS. A modeling procedure is taken to normalize the input data, and AL "tissue" is innovated to make AL more complex. GALS is anticipated to contribute significantly to the fitness of AL evolution. The formation of"tissue" begins with some different AL basic cells, and then tissue is produced by the casual selections of one or several of these cells. As a result, the gene parameters, represented by "tissues", could become highly diversified. This diversification should have obvious effects on improving gene fitness. This study took the innovative method of GALS in a stock forecasting problem under a carefully designed manipulating platform. And the researching results verify that the GALS is successful in improving the gene evolution fitness.     

片上网络GALS接口设计

本文提出了一种基于握手协议的GALS接口设计方法。该接口采用异步FIFO作为输入缓冲区,有效降低了数据传输延迟;采用环形缓冲的概念来管理缓冲区,使接口具有了可扩展性。FPGA验证结果表明,该接口保证了适配单元与网络路由之间完成准确的异步传输,4通道的接口共占用了405个ALUT（Adaptive Look-Up Table）和支持211 MHz的时钟频率。     

Elastic Flow in an Application Specific Network-on-Chip

A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network must be able to communicate between cells in di erent clock domains, and do so with minimal space, power, and latency overhead. In this paper, we describe an asynchronous NoC using an elastic-flow protocol, and methods of automatically generating a topology and router placement. We use the communication profile of the SoC design to drive the binary-tree topology creation and the physical placement of routers, and a force-directed approach to determine router locations. The nature of elastic-flow removes the need for large router bu ers, and thus we gain a significant power and space advantage compared to traditional NoCs. Additionally, our network is deadlock-free, and paths have bounded worst-case communication latencies.     

Compositionality of Statically Scheduled IP

Timing Closure in presence of long global wire interconnects is one of the main current issues in System-on-Chip design. One proposed solution to the Timing Closure problem is Latency-Insensitive Design (LID) [Luca Carloni, Kenneth McMillan, and Alberto Sangiovanni-Vincentelli. Theory of latency-insensitive design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20(no. 9):pp. 1059–1076, 2001; Mario R. Casu and Luca Macchiarulo. A new approach to latency insensitive design. In DAC'04: Proceedings of the 41st annual conference on Design automation, pages 576–581, New York, NY, USA, 2004. ACM Press].It was noticed in [Mario R. Casu and Luca Macchiarulo. A new approach to latency insensitive design. In DAC '04: Proceedings of the 41st annual conference on Design automation, pages 576–581, New York, NY, USA, 2004. ACM Press] that, in many cases, the dynamically scheduled synchronisations introduced by latency-insensitive protocols could be computed off-line as a static periodic schedule. We showed in [Julien Boucaron, Jean-Vivien Millo, and Robert De Simone. Latency-insensitive design and central repetitive scheduling. In Formal Methods and Models for Co-Design, 2006. MEMOCODE'06. Proceedings. Fourth ACM and IEEE International Conference on, pages 175–183, Piscataway, NJ, USA, 2006. IEEE Press; Julien Boucaron, Jean-Vivien Millo, and Robert De Simone. Formal methods of scheduling for latency-insensitive designs. EURASIP journal on embedded system, 2007 (not yet published)] how this schedule could then be used to further optimize the protocol resources when they are found redundant. The purpose of the present paper is to study how the larger blocks, obtained as synchronous components interconnected by LID protocols optimized by static schedule informations, can be again made to operate with an environment that provides also I/O connections at its own (synchronous or GALS) rate.We also consider the case of multirate SoC, using results from SDF (Synchronous DataFlow) theory [Edward A. Lee and David G. Messerschmitt. Synchronous data flow. Proceeding of the IEEE, vol. 75(no. 9):pp. 1235–1245, 1987].