一种新型的Pt-NiO混合敏感膜全固态 溶解CO2传感器及其特性测量

为了方便的测量溶解二氧化碳(CO₂),利用室温下NiO对CO₂的敏感特性,基于碳糊成膜方法,研制了一种新型全固态溶解CO₂传感器.文章中,分析了传感器的结构和NiO敏感膜对CO₂的敏感机理,测量了不同工作点和不同温度下传感器输出电压ΔV_rs随着溶解CO₂浓度变化的响应特性.实验结果显示,基于MISFET结构的Pt-NiO混合敏感膜溶解CO₂传感器可以在室温下方便的检测溶解CO₂浓度.     

Origin of electron mobility enhancement in (1 1 1)-oriented InGaAs channel metal-insulator-semiconductor field-effect-transistors

Electrical and physical characteristics of the Al₂O₃/InGaAs interfaces with (1 1 1)A and (1 0 0) orientations were investigated in an attempt to understand the origin of electron mobility enhancement in the (1 1 1)A-channel metal-insulator-semiconductor field-effect-transistor. The (1 1 1)A interface has less As atoms of high oxidation states as probed by X-ray photoelectron spectroscopy. The electrical measurements showed that energy distribution of the interface traps for the (1 1 1)A interface is shifted toward the conduction band as compared to that for the (1 0 0) interface. Laterally-compressed cross-section transmission electron microscopy images showed that the characteristic lengths of the interface roughness are different between the (1 1 1)A and (1 0 0) interfaces. The contributions of the Coulomb and roughness scattering mechanisms are discussed based on the experimental results.     

LT-GaAs with high breakdown strength at low temperature for power MISFET applications

Low temperature grown GaAs has been fabricated containing a limited amount of excess arsenic. The material has a low conductivity in the order of 100KΩ cm, due to hopping in a deep donor band. This σ-LT-GaAs was grown reproducibly by using the lattice mismatch as the primary parameter for substrate temperature calibration. Breakdown fields, in the order of 100kV/cm, are observed for planar structures and increased at low measurement emperatures. Low hopping conductivity and high breakdown field are also observed in the lossy dielectric metal-insulator-semiconductor field-effect transistor device using σ-LT-GaAs as a surface layer. The record radio frequency power density of 4.0W/mm at 77K is extracted from the dc output characteristics.     

On the mechanisms limiting mobility in InP/InGaAs buried channel nMISFETs

MISFETs incorporating the InP/InGaAs buried channel showed a high peak mobility of 5500 cm²/V s. Spillover of the inversion carriers from the buried channel to the MIS interface on the InP barrier layer caused drastic mobility degradation as the carrier concentration was increased. The spillover was evidenced by observing a negative transconductance and a kink in split capacitance-voltage curves. Remote scattering by the trapped charges at the MIS interface also reduced the mobility when the InP barrier layer was as thin as 2 nm.     

Electrical characterization of high-k gate dielectrics on Ge with HfGeN and GeO2 interlayers

Two kinds of HfSiO_x/interlayers (ILs)/Ge gate stack structures with HfGeN- and GeO₂-ILs were fabricated using electron cyclotron resonance (ECR) plasma sputtering and the subsequent post deposition annealing (PDA). It was found that HfGe was formed by the deposition of Hf metal on Ge and changed to HfGeN by N₂ ECR-plasma irradiation, which was used as IL. Another IL was GeO₂, which was grown by thermal oxidation at 500 °C. For dielectrics with HfGeN-IL, PDA of 550 °C resulted in effective oxide thickness (EOT) of 2.2 nm, hysteresis of 0.1 V, and interface state density (D_it) = 7 × 10¹² cm^− 2 eV^− 1. For dielectrics with GeO₂-IL, PDA of 500 °C resulted in EOT of 2.8 nm, hysteresis of 0.1 V, and D_it = 1 × 10¹² cm^− 2 eV^− 1. The structural change of HfSiO_x/GeO₂/Ge during the PDA was clarified by using X-ray photoelectron spectroscopy, and the gate stack formation for obtaining the good IL was discussed.     

Fabrication of Enhancement Mode GaN Metal-Insulator-Semiconductor Field Effect Transistor

Recently,a numberofpapers on Ga N-based field-effecttransistors(FETs) have beenreported.The metal-insulator-semiconductor technology is widely adopted in manyapplications since it can provide the high DC input impedance,large gate voltage swings,norm...     

GaAs MISFET制备中的选择性腐蚀研究

研究了体积比为1:1到10:1的50%柠檬酸/双氧水溶液对GaAs/A1 Ga1-xAs结构腐蚀的选择特性,用α台阶仪、原子力显微镜(AFM)等方法研究了腐蚀样品表面的微观形貌.利用这种选择腐蚀技术制备了undoped-GaAs/n-GaAs调制掺杂沟道金属-绝缘体-半导体场效应晶体管,获得了很好的器件特性参数,证明了这种腐蚀溶液适合于器件制备中的栅挖槽工艺.     

用于OEIC的InPMISFET的研制

用MOCVD方法生长了n+-InP/n-InP/SI-InP材料,以HfO2为介质膜,用电子束蒸发和选择化学腐蚀研制成栅宽0.002mm、栅长为0.2mm的具有蘑菇状栅极结构的InPMISFET.直流特性测量表明,跨导gm=80-115ms/mm,开启电压VT-3.62V,沟道的有效电子迁移率ueff=674cm2/V·S,界面态密度NSS=9.56×1011cm-2.设计计算的特征频率fT=97.1GHz,最高特征频率fmax=64.7GHz,尚未发现器件性能的漂移现象.本器件可作为InP基的单片光电子集成器件(OEIC)的放大部分.     

Fabrication of Enhancement Mode GaN Metal-Insulator-Semiconductor Field Effect Transistor

The enhancement mode GaN metal-insulator-semiconductor field effect transistor (E-MISFET) is successfully fabricated on a GaN/A1GaN/GaN double heterojunction structure with SiO2 as the insulator layer. The enhancement mode DC characteristics have been first achieved in the device with the gate-length of 6μm,10μm and gate-width of 100μm. The device with gate-length of 6μm shows the DC transconductance of 0.6 mS/mm and the maximum drain-source current of 0.5mA. The gate leakage current is lower than 10-6A at the bias of -10V while the gate breakdown voltage is higher than 20V. This result proves the presence of a piezoelectric field in the heterojunction,the strongly asymmetric band bending and the carriers distribution caused by the piezoelectric field.     

增强型自对准源漏区AlN/GaN/AlN 氮极化金属绝缘半导体场效应晶体管的静态特性与短沟道效应的研究

This paper aims to simulate the I–V static characteristic of the enhancement-mode(E-mode) Npolar Ga N metal–insulator–semiconductor field effect transistor(MISFET) with self-aligned source/drain regions.Firstly, with SILVACO TCAD device simulation, the drain–source current as a function of the gate–source voltage is calculated and the dependence of the drain–source current on the drain–source voltage in the case of different gate–source voltages for the device with a 0.62 m gate length is investigated. Secondly, a comparison is made with the experimental report. Lastly, the transfer characteristic with different gate lengths and different buffer layers has been performed. The results show that the simulation is in accord with the experiment at the gate length of 0.62 m and the short channel effect becomes pronounced as gate length decreases. The E-mode will not be held below a100 nm gate length unless both transversal scaling and vertical scaling are being carried out simultaneously.