Commitment-based device-pairing protocol with synchronized drawings and comparison metrics

This article presents a new method for pairing devices securely. The commitment-based authentication uses a fuzzy secret that the devices only know approximately. Its novel feature is time-based opening of commitments in a single round. We also introduce a new source for the fuzzy secret: synchronized drawing with two fingers of the same hand on two touch screens or surfaces. The drawings are encoded as strings and compared with an edit-distance metric. A prototype implementation of this surprisingly simple and natural pairing mechanism shows that it accurately differentiates between true positives and man-in-the-middle attackers.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

用CPLD实现SRAM工艺FPGA的安全应用

提出了一种利用CPLD产生的伪随机码来加密SRAM工艺FPGA的方法,并详细介绍了具体的电路和VHDL代码。     

深亚微米PD和FD SOI MOS器件热载流子损伤的研究

研究了深亚微米PD和FD SOI MOS器件遭受热截流子效应(HCE)后引起的器件参数退化的主要差异及其特点，提出了相应的物理机制，以解释这种特性。测量了在不同应力条件下最大线性区跨导退化和闽值电压漂移，研究了应力Vg对HCE退化的影响，并分别预测了这两种器件的寿命，提出了10年寿命的0．3μm沟长的PD和FD SOI MOS器件所能承受的最大漏偏压。     

深亚微米MOSFET衬底电流的模拟与分析

利用器件模拟手段对深亚微米ＭＯＳＦＥＴ的衬底电流进行了研究和分析，给出了有效的道长度，栅氧厚度，源漏结深，衬底掺杂浓度以及电源电压对深亚微米ＭＯＳＦＥＴ衬底电流的影响，发现电源电压对深亚微米ＭＯＳＦＥＴ的衬底电流有着强烈的影响，热载流子效应随电源电压的降低而迅速减小，当电源电压降低到一定程度时，热载流子效应不再成为影响深亚微米ＭＯＳ电路可靠性的主要问题。     

CCD型束流截面探测器

CCD型束流截面探测器的主要特点是使用电荷耦合器件做传感器,用束流同步光中的可见光成份做为信号源。该探测器同时具有模拟量和数字量两种输出,工作周期短,速度高,不影响束团粒子寿命,在电子储存环物理运行中,是一种有效的探测设备。     

基于VW2010芯片的嵌入式多媒体监控系统压缩/解压卡设计

在简要分析了多媒体监控系统发展现状的基础上，提出了一种基于VW2010压缩／解压芯片的多媒体压缩／解压卡的设计方案，给出了基于VW2010的多媒体监控系统压缩和解压卡的硬件结构图以及在Linux系统下VW2010的驱动程序，同时给出了在Linux Redhat7．3下编写的测试程序，并进行了全面的测试。     

浅论油液质量对机械设备运转的影响

通过分析润滑油、液压油的质量对设备运转的影响，提出了使用润滑油、液压油的几点建议。     

交变光源型位敏器件应用技术

在利用直流光源型半导体位敏器件（ＰＳＤ）进行测量时，常因环境光强的改变而引起误差。本文介绍的交变调制光源及其相应的ＰＳＤ光电信号处理电路，可大大地降低和消除杂散光对测量的影响。     

一种用于DS扩频信号非相干检测的差分延迟SAW相关器

本文介绍了用于ＤＰＳＫ调制的ＤＳ扩频信号非相干检测的一种ＳＡＷ器件的设计方法。对所研究的差分延迟功能均集于单一器件中。因为没有采用独立的延迟线，故消除了带限影响，ＤＰＳＫ解调器延迟支路无插入损耗。