Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Evaluation of performance enhancing proxies in internet over satellite

Performance enhancing proxies (PEPs) are widely used to improve the performance of TCP over high delay‐bandwidth product links and links with high error probability. In this paper we analyse the performance of using TCP connection splitting in combination with web caching via traces obtained from a commercial satellite system. We examine the resulting performance gain under different scenarios, including the effect of caching, congestion, random loss and file sizes. We show, via analysing our measurements, that the performance gain from using splitting is highly sensitive to random losses and the number of simultaneous connections, and that such sensitivity is alleviated by caching. On the other hand, the use of a splitting proxy enhances the value of web caching in that cache hits result in much more significant performance improvement over cache misses when TCP splitting is used. We also compare the performance of using different versions of HTTP in such a system. Copyright © 2003 John Wiley & Sons, Ltd.     

Universal Rendering Sequences for Transparent Vertex Caching of Progressive Meshes

We present methods to generate rendering sequences for triangle meshes which preserve mesh locality as much as possible. This is useful for maximizing vertex reuse when rendering the mesh using a FIFO vertex buffer, such as those available in modern 3D graphics hardware. The sequences are universal in the sense that they perform well for all sizes of vertex buffers, and generalize to progressive meshes. This has been verified experimentally.     

Measuring consistency in TTL-based caches

We propose a general modeling framework to evaluate the performance of cache consistency algorithms. In addition to the usual hit rate, we introduce the hit^* rate as a consistency measure, which captures the fraction of non-stale downloads from the cache. We apply these ideas to the analysis of the fixed TTL consistency algorithm in the presence of network delays. The hit and hit^* rates are evaluated when requests and updates are modeled by renewal processes. Classical results on the renewal function lead to various bounds.     

超薄SiO2层的热生长

隧道小孔中超薄ＳｉＯ２的生长是ＥＥＰＲＯＭ电路制造的关键工艺之一。采用ＳＵＰＲＥＭ－Ⅲ工艺模拟程序对超薄ＳｉＯ２的热生长进行了工艺模拟，经过大量的工艺实验及优化，确定了超薄ＳｉＯ２的最佳生长条件，生长出的ＳｉＯ２性能良好，完全可满足ＥＥＰＲＯＭ研制的要求。     

本地缓存和代理服务器环境下的网络日志挖掘

介绍了网络日志挖掘的基本概念，提出了一个网络日志挖掘通用系统的结构，分析了本地缓存和代理服务器对日志挖掘的影响，并给出了一种近似解决方案。这种方案通过网络拓扑结构和日志文件记录的结合，将杂乱无章的日志记录组合成具有语义信息的事务记录，从而使挖掘结果更有意义。     

基于i860的存储器子系统设计

微处理机系统中的存储器子系统设计对整个系统性能的高低有重要的影响，尤其当微处理器的主频越来越高时。本文结合实际例子，给出了一个基于ｉ８６０处理器（４０ＭＨｚ）的主存设计方案，讨论了实际中需仔细考虑的因素。该设计可为其它高性能ＲＩＳＣ系统设计提供参考。     

时效和重新训练对Cu－Zn－Al合金组织与记忆性能的影响

用约束训练法对时效后的Ｃｕ－Ｚｎ－Ａｌ形状记忆合金进行了重新训练。结果表明，在未发生贝氏体转变的条件下，时效所导致的记忆衰减可以通过重新训练予以改善。透射电镜分析指出，重新训练后，发生了马氏体的再取向，因时效而导致的细条状、台阶状变体大部分消除，且变体间的结合方式变为自协作性良好的孪晶关系，从而改善了合金的记忆性能。     

电容检测纱线传感器转换特性对纱线不匀率测试的影响

讨论了纱线测试中受电容检测纱线传感器转换特性的非线性影响，测得的条干不匀率值与纱线的实际条干不匀率值之间的差异，从理论上估计了纱线在不同的电容检测槽内测试时，由于其截面充满系数不同而引起的相对差异，并用试验数据加以验证。     

The Content Driven Mobile Internet

The development of future mobile networks will be driven, in large part, by content and web based services. In this paper, we examine several performance, scalability and architectural challenges faced by future mobile web applications and how advanced mobile content delivery techniques can address these challenges. We review existing content delivery using a taxonomy that consists of three categories: network scaling, end system acceleration, and content and protocol optimization. While wireline content delivery focuses on network and server scalability, mobile content delivery will likely benefit most from optimizing radio link usage. We also present our ongoing work in this area, which extends the functionality of edge caching to the terminal, uses user interest correlation information to maintain low terminal power consumption and adds a new dimension to radio resource management. This revised version was published online in August 2006 with corrections to the Cover Date.